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Description: 在ccs中调试DSP外部存储sdram的反色代码，主要是通过dsp/bios中的HST管道实现的。其中选用的是DM642芯片及MT48LC16M16A2的sdram，且sdram的相关时序参数已配置好。
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Size: 209585 |
Author: jinjingxia |
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Description: 在ccs中调试DSP外部存储sdram的反色代码，主要是通过dsp/bios中的HST管道实现的。其中选用的是DM642芯片及MT48LC16M16A2的sdram，且sdram的相关时序参数已配置好。-In ccs debug DSP external memory sdram of the anti-color code, mainly through the dsp / bios in the HST pipeline implementation. One choice is the DM642 chip and MT48LC16M16A2 the sdram, sdram and the related timing parameters have been configured.
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Size: 266240 |
Author: jinjingxia |
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Description: memory control source code
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Size: 396288 |
Author: chen |
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Description: SDram 接口verylog 程序 SDram 接口verylog 程序-SDram interface procedures verylog
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Size: 9216 |
Author: lili |
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Description: memory very useful free core
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Size: 1860608 |
Author: siluyuan |
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Description: 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
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Size: 26624 |
Author: 姜琰俊 |
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Description: SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
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Size: 3031040 |
Author: jianzi |
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Description: System will automatically delete the directory of debug and release, so please do not put files on these two directory.
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Size: 1856512 |
Author: HMin |
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Description: 硬件芯片MT48LC16M16A2的说明书 硬件芯片MT48LC16M16A2的说明书-The manual hardware chip MT48LC16M16A2
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Size: 1728512 |
Author: JAY |
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