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[VHDL-FPGA-Verilog] CPU

Description: 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft interrupt
Platform: | Size: 90112 | Author: 张超 | Hits:

[Data structs] insertsort_recursive

Description: MIPS迭代实现插入排序算法。时间复杂度和空间复杂度较低-MIPS iterations to achieve insertion sort
Platform: | Size: 1024 | Author: liupeng | Hits:

[VHDL-FPGA-Verilog] mips_project

Description: 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
Platform: | Size: 17408 | Author: yangxinghua | Hits:

[VHDL-FPGA-Verilog] MIPS32

Description: 该文档包括了mips指令集的全部指令，并且对每一条指令的执行过程做了详细的分析。-This document contains all the instructions mips instruction set, and the execution of each instruction to do a detailed analysis.
Platform: | Size: 640000 | Author: yangxinghua | Hits:

[VHDL-FPGA-Verilog] Mips_Assembly_Language_Programming

Description: 文档包含了mips汇编语言的编写规则和实例。国外的教材，内容较为详细。-Mips assembly language document contains the written rules and examples. Foreign materials, the content in more detail.
Platform: | Size: 450560 | Author: yangxinghua | Hits:

[Data structs] queen

Description: 经典的八皇后问题，采用MIPS汇编语言的实现方法。-solution of the eight queens problem by MIPS
Platform: | Size: 1024 | Author: | Hits:

[Windows Develop] DLX

Description: DLX实现，实用Visual C++编程，思想为MIPS体系结构，可以考察系统仿真的性能和指标-DLX implementation, using Visual C++.
Platform: | Size: 961536 | Author: Solomon Jee | Hits:

[VHDL-FPGA-Verilog] single_cycle

Description: single cycle mips code in vhdl
Platform: | Size: 104448 | Author: kallu | Hits:

[SCM] IOP_MIPS

Description: 8202FD CARD IOP_ MIPS
Platform: | Size: 1405952 | Author: WINDSON | Hits:

[VHDL-FPGA-Verilog] project

Description: s-stage MIPS pipeline with forwarding unit implemented in quartus ||
Platform: | Size: 1978368 | Author: tootaa | Hits:

[Other Embeded program] cn_ATmega8

Description: 产品特性 • 高性能、低功耗的 8 位 AVR® 微处理器 • 先进的 RISC 结构 – 130 条指令 – 大多数指令执行时间为单个时钟周期 – 32 个 8 位通用工作寄存器 – 全静态工作 – 工作于 16 MHz 时性能高达 16 MIPS – 只需两个时钟周期的硬件乘法器 • 非易失性程序和数据存储器 – 8K 字节的系统内可编程 Flash 擦写寿命 : 10,000 次 – 具有独立锁定位的可选 Boot 代码区通过片上 Boot 程序实现系统内编程真正的同时读写操作 – 512 字节的 EEPROM 擦写寿命 : 100,000 次 – 1K 字节的片内 SRAM – 可以对锁定位进行编程以实现用户程序的加密 -Features • High performance, low-power AVR ® 8-bit microprocessor • Advanced RISC Architecture - 130 Powerful Instructions- Most Single Clock Cycle Execution Time - 32 x 8-bit general purpose working registers - Fully Static Operation
Platform: | Size: 2177024 | Author: li | Hits:

[Software Engineering] ourdev_486505

Description: MIPS CPU的USB转EJTAG接口的原理图，并且带有一个串口电路-MIPS CPU s USB to EJTAG interface schematics, and with a serial circuit
Platform: | Size: 53248 | Author: 吴亚杰 | Hits:

[VHDL-FPGA-Verilog] Multiplier-shifter-design-tradeoffs-in-a-32-bit-m

Description: excellent paper which is about the design of MIPS Architecture in the field of computer science and technology
Platform: | Size: 746496 | Author: trial6 | Hits:

[VHDL-FPGA-Verilog] code

Description: this a muti cycle mips code that it can do mutiply,add,sub,xor,beq,bne,slt,sltu,ori,xori and... and it take address and data and then operate on them.-this is a muti cycle mips code that it can do mutiply,add,sub,xor,beq,bne,slt,sltu,ori,xori and... and it take address and data and then operate on them.
Platform: | Size: 5120 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] multi_cycle_Verilog

Description: this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less than 32 bits in 32 clocks .
Platform: | Size: 4096 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] VHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

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