Description: Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft interrupt
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........\barrier.vhd
........\cache.vhd
........\cpu.bit
........\CPU.vhd
........\data_bypass.vhd
........\executor.vhd
........\instruction_decoder.vhd
........\memory.vhd
........\reg_controller.vhd
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