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Description: ldpc码的经典程序,针对ldpc自适应调制的码率变换-ldpc code classical procedures against ldpc adaptive modulation rate of transformation
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Size: 1024 |
Author: liu |
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Description: The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
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Size: 299008 |
Author: sandeep |
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Description: Sphere Decoder : an m-file to perform sphere decoding
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Size: 8192 |
Author: Saeed |
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Description: MIMO系统采用QR检测算法的MATLAT仿真程序-mimo qr
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Size: 1024 |
Author: suideliang |
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Description: 书名：LDPC原理与应用。是国内第一本介绍用LDPC编、译码基本原理及应用技术的一本书。对用 vhdl 或verilog实现硬件编程LDPC的人开发无线通信是很好的资料-Title: LDPC Principles and Applications. Is the first book describes using LDPC Encoding and Decoding the basic principles and application of technology, a book. Right to use vhdl or verilog hardware programming LDPC people to achieve development of wireless communications is a very good information
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Size: 8414208 |
Author: 邓军 |
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Description: mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过-mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on
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Size: 2194432 |
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Description: MIMO Simulation VHDL code
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Size: 80896 |
Author: Anuj |
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Description: Verilog Code for MIMO system
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Size: 97280 |
Author: Anuj |
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Description: the code is about ML detector of mimo technology ,,,,we need of vhdl code for all detectors
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Size: 5120 |
Author: bhagyalaxmi |
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Description: A one-dimensional transfer matrix method to calculate the phonon crystal structure, MIMO OFDM matlab simulation, For time-frequency analysis algorithm.
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Size: 59392 |
Author: fanfingsing
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Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers
etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm
(FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different
topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and
shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder,
carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective
is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative
study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on
the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis
of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is
used to implement the proposed designs in VHDL.
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Size: 1123027 |
Author: nalevihtkas |
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