Description: The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
- [CACHE] - This document details the working princi
- [CacheDemo] - Computer system architecture for multi-C
- [mipscpudesign] - cpu design example mips. MIPSI instructi
- [8080cpu] - this is code for cpu 8080 design
- [dCACHE] - Vhdl write data cache
- [iCACHE] - To use VHDL to write the data cache, bas
- [P6_Cache] - MEMORY CACHE SIMPLE CODE
File list (Check if you may need any files):
project1_report1.doc
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