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[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[Communication-Mobile] gardner_simulink

Description: 位同步gardner 算法的simulink仿真-bit synchronization algorithm simulink
Platform: | Size: 23552 | Author: 陆军 | Hits:

[SCM] MACPHY

Description: 802.15.4协议的物理层和mac层的源码-802.15.4 physical layer and mac layer source
Platform: | Size: 35840 | Author: 赵彦 | Hits:

[VHDL-FPGA-Verilog] 05805

Description: 无线通信fpga设计matlab、verilog代码
Platform: | Size: 205824 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] adpll

Description: 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
Platform: | Size: 2048 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] farrow

Description: 一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
Platform: | Size: 7234560 | Author: 左洪成 | Hits:

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