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[Other] lpcinterface

Description: lpc源代码verilog实现的。操作low pin count设备-LPC realize the Verilog source code. Operation of low pin count devices
Platform: | Size: 1024 | Author: 毛军捷 | Hits:

[VHDL-FPGA-Verilog] lpc

Description: LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
Platform: | Size: 5120 | Author: 饶进平 | Hits:

[Communication-Mobile] wb_lpc_latest.tar

Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Platform: | Size: 410624 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] Vme_Interface

Description: 这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file
Platform: | Size: 2688000 | Author: zhangsongbai | Hits:

[VHDL-FPGA-Verilog] LPC2DDR2

Description: Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array -Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array
Platform: | Size: 8192 | Author: 吴羽中 | Hits:

[VHDL-FPGA-Verilog] LPC_Peri

Description: LPC总线中目标机的vhdl代码，Low pins bus-Low pins bus
Platform: | Size: 3072 | Author: fpgabo | Hits:

[VHDL-FPGA-Verilog] LPC_Host

Description: LPC总线，主机模块代码，VHDL语言描述-LPC bus, the host code, VHDL language description
Platform: | Size: 2048 | Author: fpgabo | Hits:

[VHDL-FPGA-Verilog] module_lpc

Description: LPC接口的VHDL语言实现，可以用于TPM的开发，以及基于FPGA的设计-LPC interface language realization of VHDL, can be used for the development of the TPM, as well as the design based on FPGA
Platform: | Size: 2048 | Author: jack | Hits:

[Other] LPCSPEC

Description: LPC总线规范，2002年8月1.1版，VHDL、固件编程必看-LPC bus specification, version 1.1 in August 2002, VHDL, firmware programming must see
Platform: | Size: 380928 | Author: 张程序 | Hits:

[VHDL-FPGA-Verilog] LPC-program-CPLD

Description: 使用quartus开发。该程序通过VHDL语言实现了LPC时序。控制了2个LED数码管，通过读取LPC总线的上BIOS的数据，实现了计算机排故的POST卡功能。-Use quartus development. The program through the VHDL language to achieve a LPC timing. Control of the two LED digital tube, by reading the BIOS on the LPC bus data to achieve a computer troubleshooting a POST card function.
Platform: | Size: 304128 | Author: 赵 | Hits:

[VHDL-FPGA-Verilog] lpc_peri

Description: LPC periph，VHDL and verilog version design， lattice
Platform: | Size: 5120 | Author: Sean Wu | Hits:

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