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Description: 乘法器的实现，两种方法，调用IPcore及手动编写，基于ISE软件下的VHDL语言实现-Multiplier realization of the two methods, called IPcore and manually prepared, based on the ISE software to achieve the VHDL language
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Size: 992256 |
Author: 望天 |
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Description: 简要介绍了数字下变频的设计，通过采用xilinx的ise软件，ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
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Size: 2578432 |
Author: 望天 |
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Description: XILINX公司ISE自带的IP核，功能介绍，如何使用这些IP核来加快你的开发。-IP release note guide
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Size: 162816 |
Author: 老刘 |
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Description: altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
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Size: 896000 |
Author: panzhijian |
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Description: Xilinx12.3和12.4 license 加强版支持更多ipcore 以及modelsim编译ise 库的方法说明-Xilinx12.3 and 12.4 license as well as enhanced support for more ipcore modelsim compile ise description of the ways library
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Size: 1235968 |
Author: 王垚 |
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Description: 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed description. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
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Size: 503808 |
Author: 刘明 |
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Description: 通过调用ISE中的fft IPcore实现了fft计算，输入数据通过textio从文本文件读入，处理后的数据再读入文本中。由于数据精度问题，与MATLAB计算的结果存在一定的误差-By calling the ISE of FFT IPcore implements the FFT computation, the input data through textio read a text file, after processing the data to read the text again.Due to the data accuracy, and MATLAB calculation result has certain error
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Size: 6157312 |
Author: 靳 |
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Description: USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
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Size: 5345280 |
Author: 赵海峰 |
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