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[VHDL-FPGA-Verilog] simple_pic

Description: 简单可编程中断控制器，利用定时计数器的中断请求信号输出中断使能控制信号。-Simple Programmable Interrupt Controller, using regular counter interrupt request signal output enable control signal interruption.
Platform: | Size: 3072 | Author: 李利歌 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.
Platform: | Size: 5120 | Author: gab | Hits:

[VHDL-FPGA-Verilog] digital6counter_top

Description: 文件描述的是VHDL语言实现的16位计数器，可用于实现时钟的分频或中断控制-Document describes the VHDL language to achieve 16-bit counter can be used to achieve clock frequency or interrupt control
Platform: | Size: 1024 | Author: 杨伟军 | Hits:

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