Description: Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.
- [project4] - A 14-stage FIR filter design, has given
File list (Check if you may need any files):
6\clk.vhd
.\count.vhd
.\etu_clk.vhd
.\etu_clk_tb.vhd
.\home6_timer.vhd
.\home6_timer_tb.vhd
.\move.vhd
.\re_wr.vhd
6
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