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[GDI-Bitmap] verilog_interleave1

Description: 里面是5个关于交织器的源代码，有兴趣的可以下来学习一下-There is a 5 on the interleaver of the source code, are interested in learning what can be down
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[VHDL-FPGA-Verilog] veriloginterleave2

Description: 交织器的在5个源代码，:-) 对学习交织器真的很有用的啊 -Interleaver in 5 source code, :-) learning interleaver ah really useful
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[Software Engineering] 3GPP

Description:
Platform: | Size: 44032 | Author: hamza | Hits:

[Other] FPGA_interleaver

Description: 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
Platform: | Size: 120832 | Author: xx | Hits:

[VHDL-FPGA-Verilog] interlace

Description: 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can also be deinterleaving deinterleaving pattern, the same algorithm.
Platform: | Size: 1024 | Author: 源天 | Hits:

[VHDL-FPGA-Verilog] INTERLEAVER

Description: 1/3,k=9的卷积码VHDL实现,在xilinx ise上仿真成功。-1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
Platform: | Size: 1024 | Author: 杨胜丰 | Hits:

[Modem program] interleaver

Description: In this case is a interleaving algorithm code for deinterleaving the code, using VHDL language. This code provide the method of interleaving of the convolutioned code
Platform: | Size: 6144 | Author: kimdaeyoung | Hits:

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