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[VHDL-FPGA-Verilogentropy_coding

Description: 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His description of coding (entropy coding) for image compression test files are encoded
Platform: | Size: 19456 | Author: 周信均 | Hits:

[Graph programsobel

Description: 图像边缘检测的VERILOG实现,能准确检测图像边缘-Image Edge Detection of Verilog realize that can accurately detect image edge
Platform: | Size: 589824 | Author: 李永杰 | Hits:

[VHDL-FPGA-Verilogsobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-VerilogVIP_RAW2RGB2Gray_Medium_Sobel_Erosion_Dilation

Description: 通过纯HDL逻辑实现,对ov7725摄像头进行图像采集,存储,处理,包括中值滤波,边缘检测等经典图像算法实现(Through the realization of pure HDL logic, image acquisition, storage and processing of ov7725 camera, including median filtering, edge detection and other classic image algorithms.)
Platform: | Size: 931840 | Author: SakuraForever | Hits:

[VHDL-FPGA-Verilogsobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测,工程文件可在quartus13.1以上版本打开;工程使用到ram、fifo、pll三种ip核,design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块,sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果;测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化,再将生成文件中数据用串口发给FPGA,边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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