Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis
2. fpga implemention of a median filter
3. fpga implementation of digital filters
4.hardware acceleration of edge detection algorithm on fpgas
5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages
6. implementing 2D median filter in fpgas
7.视频图像处理与分析的网络资源 Platform: |
Size: 1969152 |
Author:carol |
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Description: Abstract—This paper proposes a new technique for face detection
and lip feature extraction. A real-time field-programmable
gate array (FPGA) implementation of the two proposed techniques
is also presented. Face detection is based on a naive Bayes classifier
that classifies an edge-extracted representation of an image. Using
edge representation significantly reduces the model’s size to only
5184 B, which is 2417 times smaller than a comparable statistical
modeling technique, while achieving an 86.6 correct detection
rate under various lighting conditions. Lip feature extraction uses
the contrast around the lip contour to extract the height and width
of the mouth, metrics that are useful for speech filtering. The
proposed FPGA system occupies only 15 050 logic cells, or about
six times less than a current comparable FPGA face detection
system.-Abstract—This paper proposes a new technique for face detection
and lip feature extraction. A real-time field-programmable
gate array (FPGA) implementation of the two proposed techniques
is also presented. Face detection is based on a naive Bayes classifier
that classifies an edge-extracted representation of an image. Using
edge representation significantly reduces the model’s size to only
5184 B, which is 2417 times smaller than a comparable statistical
modeling technique, while achieving an 86.6 correct detection
rate under various lighting conditions. Lip feature extraction uses
the contrast around the lip contour to extract the height and width
of the mouth, metrics that are useful for speech filtering. The
proposed FPGA system occupies only 15 050 logic cells, or about
six times less than a current comparable FPGA face detection
system. Platform: |
Size: 28409856 |
Author:ramanaidu |
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Description: 基于DE2-70的摄像头图像处理程序，主要在边缘检测上增加了视线内黑线判断的功能-Based on the DE2-70 camera image-processing program, mainly in the edge detection increased the black line within the line of sight to determine the function Platform: |
Size: 6322176 |
Author:liliang |
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Description: 用VHDL编写的一个按键检测的例子，采用了防抖，每按一下按键，输出一个按键脉冲。-Examples of VHDL prepared by the detection of a button, using the image stabilization, each key is pressed, the output pulse of a button. Platform: |
Size: 210944 |
Author:xuegamgma |
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Description: 基于VHDL图像边缘检测，可在在仿真波形上看出其边界值(Based on VHDL image edge detection, the boundary value can be seen on the simulation waveform) Platform: |
Size: 4808704 |
Author:吖吖啊啊 |
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Search - image detection vhdl