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[SourceCode] IEEE 802.11 模型的源码 DL : 3: 基于IEEE 802.11的MATLAB源码，里面有详细的仿真和指导
Date : 2012-03-12 Size : 82.41kb User : yutongtong@ucla.edu
[Other resource] 2012年6月29日发布SCI收录的IEEE期刊影响因子排名 DL : 0: 2012年6月29日发布SCI收录的IEEE期刊影响因子排名
Date : 2012-06-29 Size : 65kb User : 120015427@qq.com
[Documents] IEEE 802.3 Cyclic Redundancy Check v1.0 DL : 0: IEEE 802.3规定的CRC算法解释说明，pdf版本-the CRC algorithm explanation, pdf version
Date : 2025-07-02 Size : 78kb User : 马歌
[Other Embeded program] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE DL : 0: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar-IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Date : 2025-07-02 Size : 372kb User : 王刚
[SCM] IEEE 1394 火线协议标准 DL : 0: IEEE 1394 火线协议标准-IEEE 1394 FireWire protocol standards
Date : 2025-07-02 Size : 1.23mb User : 彭伟民
[Streaming Mpeg4] h.264搜索算法相关IEEE论文 DL : 0: 介绍h.264搜索算法的IEEE论文20篇-recommend 20 books of discourse h.264 grabble arithmetic IEEE.
Date : 2025-07-02 Size : 5.18mb User : 马骏
[VHDL-FPGA-Verilog] 1076 IEEE Standard VHDL Language Reference Manual. DL : 0: 1076-2002 IEEE Standard VHDL Language Reference Manual-1076-2002 IEEE Standard VHDL Language Ref validated Manual
Date : 2025-07-02 Size : 847kb User : 巫涛
[Industry research] IEEE std 1363-2000 DL : 0: IEEE所制定的椭圆曲线算法标准，对椭圆曲线算法感兴趣的朋友可以看看。-developed by the IEEE elliptic curve algorithm standard algorithm for elliptic curve interested friends can see.
Date : 2025-07-02 Size : 1.14mb User : 张进
[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE) DL : 0: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Date : 2025-07-02 Size : 175kb User : 李中伟
[Other] IEEE.Xplore.CHINESE.Ver.1.4 DL : 0: IEEE Xplore CHINESE Ver 1.4.doc IEEE Xplore CHINESE Ver 1.4.doc-IEEE Xplore ENGLISH Ver 1.4.doc IEEE Xplor e ENGLISH Ver 1.4.doc IEEE Xplore ENGLISH Ver 1. 4.doc
Date : 2025-07-02 Size : 25kb User : hang
[Other] IEEE DL : 0: 关于联合信源信道编码的文章，来自IEEE，对于JSCC的研究很有参考价值-On the joint source-channel coding of the article, from IEEE, for the study of JSCC valuable
Date : 2025-07-02 Size : 7.56mb User : Airs
[Software Engineering] MCTF(IEEE) DL : 0: IEEE上2篇较新的关于MCTF(运动补偿时域滤波)的原文文章-IEEE on two relatively new on the MCTF (Motion-compensated time-domain filtering) of the original article
Date : 2025-07-02 Size : 3mb User : 周鹏
[Technology Management] IEEE-paper-about-WEB-server DL : 0: embedded web server IEEE paper
Date : 2025-07-02 Size : 9.51mb User : 潘应云
[Multimedia program] IEEE-circuits-and-systems-for-video-technology-200 DL : 0: IEEE H.264SVC扩展专辑。全部是权威人物撰写-IEEE H.264SVC expansion album. Authority figures are all written
Date : 2025-07-02 Size : 18.7mb User : snazio
[Special Effects] IEEE DL : 0: IEEE检索的一些数字水印方面的文章，包括图像视频音频水印，涉及算法、协议等重要方面。-IEEE retrieval of some aspects of digital watermarking article, including images video audio watermarking, involving algorithms, protocol and other important aspects.
Date : 2025-07-02 Size : 10.86mb User : 王奔
[Special Effects] ieee DL : 0: 国外几篇IEEE数字水印论文.rar 希望你们能喜欢,着很不错啊-IEEE Digital Watermarking several foreign papers. Rar hope you will like it, a very错啊
Date : 2025-07-02 Size : 2.58mb User : 肖文
[Special Effects] IR(IEEE)Part1 DL : 0: 8篇经典的英文图像检索论文。都是在IEEE上下载的，每篇价值都在25美元左右。非常值得一看。-Eight classic English image retrieval papers. IEEE are downloaded, Each values are at 25 dollars. A must see.
Date : 2025-07-02 Size : 2.49mb User : Bill
[Program doc] IEEE DL : 0: IEEE papers for wireless sensor network-IEEE papers for wireless sensor network
Date : 2025-07-02 Size : 979kb User : atul
[VHDL-FPGA-Verilog] IEEE.Standard.Verilog.Hardware.Description.Languag DL : 0: IEEE Standard Verilog Hardware Description Language-IEEE Standard Verilog Hardware Description Language(
Date : 2025-07-02 Size : 2.08mb User : liukai
[Other] IEEE-paper-format-summary DL : 0: 该文档详细说明了IEEE论文格式的各种要求，说明部分为中文，结尾富有IEEE英文范文一篇。-This document detail the IEEE paper format, explains the various requirements of the part to be Chinese, ending rich IEEE English essays an article
Date : 2025-07-02 Size : 449kb User : xiaozhu

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