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Description: 基于fpga的JPEG编解码器设计，采用流水线优化解决时间并行性问题，提高DCT/IDCT模块的运行速度。-based fpga JPEG codec design, the flow of time to solve optimization problems in parallel, enhance DCT / IDCT module of the operating speed.
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Size: 6896091 |
Author: Janke |
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Description: 基于fpga的JPEG编解码器设计，采用流水线优化解决时间并行性问题，提高DCT/IDCT模块的运行速度。-based fpga JPEG codec design, the flow of time to solve optimization problems in parallel, enhance DCT/IDCT module of the operating speed.
Platform: |
Size: 6895616 |
Author: Janke |
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Description: 2维DCt源码，可以实现8乘8点数据的2维DCT变换
-2-D DCT-source, you can realize 8 x 8 data 2-D DCT transform
Platform: |
Size: 5120 |
Author: jz |
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Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
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Size: 29696 |
Author: caesar |
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