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Description: 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
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Size: 62464 |
Author: yangj2 |
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Description: ISO/IEC13239,Information technology-Telecommunications and information exchange between systems-High level data link control(HDLC) procedures-ISO/IEC13239, Information technology-Telecommunications and information exchange between systems-High level data link control (HDLC) procedures
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Size: 1386496 |
Author: lyj |
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Description: 这是一个将HDLC协议运用到串口通信的程序源码 很有参考价值-This is an HDLC serial port communication protocol used in the procedure useful reference source
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Size: 727040 |
Author: nameblue |
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Description: HDLC在通讯设备中占有重要地位，本文件提供了完整正确的HDLC的硬件逻辑设计！对设计和学习都具有参考价值-HDLC in the communications equipment plays an important role, this document is to provide a complete hardware HDLC correct logic design! Design and learning have a reference value
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Size: 177152 |
Author: 欧阳秋 |
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Description: hdlc专用芯片St5465的linux操作系统下的驱动程序，在s3c2410的环境下验证通过。-hdlc ASIC St5465 under the linux operating system driver, in the circumstances to verify s3c2410 through.
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Size: 33792 |
Author: 张权 |
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Description: a verilog code for hdlc controller
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Size: 1024 |
Author: meysam |
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Description: Freescale PowerPC 8247芯片QMC模块的HDLC驱动程序源代码-Freescale PowerPC 8247 chip HDLC module QMC driver source code
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Size: 16384 |
Author: victor |
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Description: this part of IEC 62056 standard, HDLC protocl standard-this is part of IEC 62056 standard, HDLC protocl standard
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Size: 403456 |
Author: Rama Rao |
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Description:
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Size: 47104 |
Author: fang |
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Description: VxWorks HDLC drivers for variuos platforms.
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Size: 32768 |
Author: soumendra |
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Description: 可以实现HDLC帧结构中的添零功能，使得信息部分不会和HDLC帧头部分混淆。-can insert zero to the hdlc frame,
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Size: 1024 |
Author: 王瑜 |
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Description: 他可以完成HDLC帧的删零功能，使得收端能够正确的恢复出HDLC中携带的信息-it can delete the zero from the HDLC frame ,make the information correct.
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Size: 1024 |
Author: 王瑜 |
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Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface
- use external RX and TX clocks
- Start and end of frame pattern generation
- Start and end of frame pattern checking
- Idle pattern generation and detection (all ones)
- Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
- Zero insertion
- Abort pattern generation and checking
- Address insertion and detection by software
- CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)
- FIFO buffers and synchronization (External)
- Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
- Q.921, LAPB and LAPD compliant.
- For complete specifications refer to spec document
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Size: 188416 |
Author: |
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Description: DLMS IEC 62056-46, HDLC layer, first edition
year: 2002
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Size: 3084288 |
Author: jackavenger |
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Description: hdlc帧接收器包含文件 设计代码测试代码综合脚步说明文档-hdlc receiver code.
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Size: 448512 |
Author: leizi |
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Description: 与地铁牵引系统通信的HDLC数据的CRC程序-Communication with the MTR traction system HDLC data CRC program
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Size: 2048 |
Author: 文梁 |
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Description: 高级链路控制的HDLC发送，写的还行，需要使用93版本的VHDL格式-Advanced Link Control HDLC to send, write that still need to use the 93 version of the VHDL format
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Size: 3072 |
Author: 宋珂 |
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Description: 一个老外写的HDLC协议，包括说明文件，很有参考价值-Written by a foreigner HDLC protocols, including documentation, of great reference value
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Size: 218112 |
Author: 宋珂 |
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Description: HDLC很详细的讲解资料，外面都没有的。看完可进行hdlc设计-hdlc prototypes
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Size: 109568 |
Author: 何正文 |
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Description: MPC8272 HDLC test Code
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Size: 36864 |
Author: Amit Sharma |
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