Search - floating point adder in verilog

[VHDL-FPGA-Verilog] fadd

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[Linux-Unix] fpadd

Description: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Platform: | Size: 12288 | Author: 孟军 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] fpufiles

Description: floating point adder mul and sub in verilog code
Platform: | Size: 19456 | Author: khosro raja | Hits:

[VHDL-FPGA-Verilog] float

Description: 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
Platform: | Size: 1024 | Author: 朱文 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] fadd

[Linux-Unix] fpadd

[VHDL-FPGA-Verilog] Floating-Point-Adder

[VHDL-FPGA-Verilog] fpufiles

[VHDL-FPGA-Verilog] float

CodeBus www.codebus.net