Search - floating point adder

[VHDL-FPGA-Verilog] vhdldesign

Description: 浮点加法器的VHDL算法设计浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Platform: | Size: 202752 | Author: yan | Hits:

[VHDL-FPGA-Verilog] ADD_Float_IEEE754

Description: IEEE754 floating point adder
Platform: | Size: 6144 | Author: 洪瑞徽 | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
Platform: | Size: 1024 | Author: 蔡大 | Hits:

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[VHDL-FPGA-Verilog] add(FLP)

Description: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Platform: | Size: 10240 | Author: TTJ | Hits:

[Linux-Unix] fpadd

Description: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Platform: | Size: 12288 | Author: 孟军 | Hits:

[VHDL-FPGA-Verilog] floating-point-adder1

Description: 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
Platform: | Size: 9216 | Author: Rosen | Hits:

[MiddleWare] ADDER

Description: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
Platform: | Size: 278528 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] floating_point_adder

Description: 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
Platform: | Size: 1024 | Author: 钟毓秀 | Hits:

[Windows Develop] fpadd

Description: Floating point adder
Platform: | Size: 10240 | Author: Shani Kumar Goutam | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[JSP/Java] Adder

Description: GUI方法的浮点数加法器实例，运用了textfield和button-GUI method of floating-point adder instance, use the textfield and the button
Platform: | Size: 1024 | Author: 龚恺 | Hits:

[Other] fp_adder

Description: floating point adder
Platform: | Size: 1024 | Author: sirahbizu | Hits:

[VHDL-FPGA-Verilog] adder_fp

Description: Floating Point adder
Platform: | Size: 1024 | Author: zhun6624 | Hits:

[Other] Fixed-Floating-Point-Adder-Multiplier-master

Description: Fixed-Floating-Point-Adder-Multiplier with test bench
Platform: | Size: 9216 | Author: liki20 | Hits:

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[VHDL-FPGA-Verilog] vhdldesign

[VHDL-FPGA-Verilog] ADD_Float_IEEE754

[VHDL-FPGA-Verilog] flowadd

[VHDL-FPGA-Verilog] fadd

[VHDL-FPGA-Verilog] add(FLP)

[Linux-Unix] fpadd

[VHDL-FPGA-Verilog] floating-point-adder1

[MiddleWare] ADDER

[VHDL-FPGA-Verilog] floating_point_adder

[Windows Develop] fpadd

[VHDL-FPGA-Verilog] Floating-Point-Adder

[JSP/Java] Adder

[VHDL-FPGA-Verilog] fpufiles

[VHDL-FPGA-Verilog] floating-point-adder

[VHDL-FPGA-Verilog] 32-float-point-adder

[VHDL-FPGA-Verilog] a-floating-point-adder

[VHDL-FPGA-Verilog] floating-point-adder-subtractor

[Other] fp_adder

[VHDL-FPGA-Verilog] adder_fp

[Other] Fixed-Floating-Point-Adder-Multiplier-master

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