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Description: 这文章授予您要诀关于怎样有浮动SIP 控制在您的口袋PC/Windows CE NET 设备里。同时, 您有学会关于怎样对做软的重新设置(没有按任何个按钮) 在您的设备。-This article gives you tips on how to control the floating SIP in your pocket PC / Windows CE NET equipment Lane. Meanwhile, you have to learn about how to do the soft reset (not any buttons) in your equipment.
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Size: 19826 |
Author: Nell |
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Description: 浮点复数基2时分FFT完成适当的FFT,输出改写输入缓冲器。-floating-point complex FFT-based two hours to complete the FFT output rewritten input buffer.
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Size: 1440 |
Author: minytian |
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Description: ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
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Size: 19010 |
Author: 李里 |
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Description: 51单片机浮点数运算子程序及IEEE和51浮点数相互转换程序 -51 floating-point operations and subroutine IEEE floating point and 51 mutual conversion
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Size: 5120 |
Author: 阿呆 |
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Description: ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
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Size: 18432 |
Author: |
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Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
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Size: 1024 |
Author: 张桓铭 |
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Description: msp430浮点库,浮点运算很好的例子!-Controller floating point libraries, floating-point operations a good example!
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Size: 90112 |
Author: 赵春福 |
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Description: 各种51单片机源程序集,包括浮点数的计算,多字节的加减等算法的实现-SCM source scripts, including floating point calculations, multi-byte such as addition and subtraction algorithm implementation
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Size: 125952 |
Author: 周云 |
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Description: 这代码是将Tab Ctrl添加到浮动窗口。-This code is added to the Tab Ctrl floating window.
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Size: 83968 |
Author: 徐小村 |
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Description: 这文章授予您要诀关于怎样有浮动SIP 控制在您的口袋PC/Windows CE NET 设备里。同时, 您有学会关于怎样对做软的重新设置(没有按任何个按钮) 在您的设备。-This article gives you tips on how to control the floating SIP in your pocket PC/Windows CE NET equipment Lane. Meanwhile, you have to learn about how to do the soft reset (not any buttons) in your equipment.
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Size: 19456 |
Author: Nell |
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Description: 浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
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Size: 202752 |
Author: yan |
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Description: 浮点复数基2时分FFT完成适当的FFT,输出改写输入缓冲器。-floating-point complex FFT-based two hours to complete the FFT output rewritten input buffer.
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Size: 1024 |
Author: minytian |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
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Size: 179200 |
Author: 李中伟 |
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Description: 利用FPGA实现浮点运算的verilog代码
希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
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Size: 130048 |
Author: jake |
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Description: This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.-This lab exercise will introduce you to Acc elDSP's floating-to fixed-point conversion f eatures. AccelDSP will automatically generat e a fixed-point representation of a floating-p oint design. This process is controllable by us ing quantize directives.
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Size: 26624 |
Author: 杨平 |
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Description: 该文档主要讲述dsp芯片中进行定点运算所设计的基本问题,分别介绍了定标、从浮点到定点的运算,定点的快速运算及其实现。文档中举出大量的例子说明,相信下载阅读后肯定会很有收获。-the document focuses on the dsp chip sentinel operation designed the basic problem introduced calibration, from floating-point to fixed-point arithmetic, fixed-point operations and the rapid realization. Documents cite a lot of examples, I believe that after reading the download will certainly learned a great deal.
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Size: 270336 |
Author: 王大雷 |
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Description: 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
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Size: 9216 |
Author: Rosen |
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Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
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Size: 154624 |
Author: 凌音 |
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Description: verilog implementation of the floating point adder
Platform: |
Size: 2048 |
Author: ramtin |
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Description: verilog implementation of the floating point multiplier
Platform: |
Size: 1024 |
Author: ramtin |
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