Search - flip flop vhdl

[VHDL-FPGA-Verilog] djkrs

Description: d,jk,rs触发器的vhdl语言实现，简单明了-d, jk, rs flip-flop of the VHDL language, simple and clear
Platform: | Size: 70656 | Author: 周军 | Hits:

Description: 32×32的寄存器堆，它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成，最低层次的模块是D触发器，中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器，顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法，先用行为建模方法建立低层模块，然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
Platform: | Size: 4096 | Author: 甜 | Hits:

[VHDL-FPGA-Verilog] mimasuo

Description: vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验报告 verilog rs触发器 vhdl实验-Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
Platform: | Size: 97280 | Author: wan | Hits:

[VHDL-FPGA-Verilog] bhgfdti

Description: 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step addition and subtraction counter
Platform: | Size: 423936 | Author: 俞皓尹 | Hits:

[VHDL-FPGA-Verilog] tristate

Description: VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
Platform: | Size: 1024 | Author: Davood | Hits:

[Other] jk-ff

Description: j-k flip flop implementation in XCS2-j-k flip flop implementation in XCS200
Platform: | Size: 15360 | Author: Amirali | Hits:

[VHDL-FPGA-Verilog] jkff

Description: JK flip-flop is implemented using VHDL
Platform: | Size: 39936 | Author: nik | Hits:

[VHDL-FPGA-Verilog] vhdl_jk

Description: 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
Platform: | Size: 201728 | Author: 刘轶龙 | Hits:

[VHDL-FPGA-Verilog] rs_1

Description: rs触发器的设计，是用vhdl实现的，欢迎下载。-rs flip-flop design is achieved using vhdl.
Platform: | Size: 21504 | Author: Mr zhang | Hits:

[Windows Develop] DtoJK

Description: Using an edge triggered D flip-flop to implement a JK flip-flop
Platform: | Size: 3072 | Author: PigeonLove Purrrrr | Hits:

[ELanguage] 5

Description: Code for JK flip flop and SR flip flop
Platform: | Size: 1024 | Author: D S Manjunath | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
Platform: | Size: 1024 | Author: 龚成 | Hits:

[Other] cnt8

Description: 用JK-flip-flop做的8进制counter-mod-8-counter
Platform: | Size: 385024 | Author: suhang | Hits:

[VHDL-FPGA-Verilog] srandDflipflop

Description: this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 205824 | Author: jatab | Hits:

[FlashMX] count10

Description: 十进制计数器自己尝试编辑的，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can-Decimal counter his attempt to edit, and can-jk flip-flop, try to edit their own, using state machine to achieve, you can
Platform: | Size: 106496 | Author: liu jian ming | Hits:

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[VHDL-FPGA-Verilog] djkrs

[GIS program] register

[VHDL-FPGA-Verilog] mimasuo

[VHDL-FPGA-Verilog] bhgfdti

[VHDL-FPGA-Verilog] tristate

[Other] jk-ff

[VHDL-FPGA-Verilog] jkff

[VHDL-FPGA-Verilog] vhdl_jk

[VHDL-FPGA-Verilog] rs_1

[Windows Develop] DtoJK

[ELanguage] 5

[VHDL-FPGA-Verilog] vhdl

[Other] cnt8

[VHDL-FPGA-Verilog] srandDflipflop

[FlashMX] count10

[VHDL-FPGA-Verilog] D_flip

[VHDL-FPGA-Verilog] vhdl-code-for-jk-flip-flop

[VHDL-FPGA-Verilog] JK-flip-flop

[assembly language] D-FLIP-FLOP

[VHDL-FPGA-Verilog] project.map

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