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Title: JK-flip-flop Download
  • Category:
  • VHDL-FPGA-Verilog
  • Tags:
  • File Size:
  • 15kb
  • Update:
  • 2013-07-02
  • Downloads:
  • 0 Times
  • Uploaded by:
  • chen
 Description: Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language
 Downloaders recently: [More information of uploader chen]
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带有异步置位复位端的上升沿触发的JK触发器\cyjkff.flow.rpt
........................................\cyjkff.map.rpt
........................................\cyjkff.map.summary
........................................\cyjkff.qpf
........................................\cyjkff.qsf
........................................\cyjkff.qws
........................................\cyjkff.vhd
........................................\cyjkff_assignment_defaults.qdf
........................................\db\cyjkff.db_info
........................................\..\cyjkff.eco.cdb
........................................\..\cyjkff.sld_design_entry.sci
........................................\db
带有异步置位复位端的上升沿触发的JK触发器
    

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