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[Other resourcebyvhdstopwatchl

Description: 1.高精度数字秒表(0.01秒的vhdl语言实现) 2.具有定时,暂停,按键随机存储,翻页回放功能; 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔,可控性高。 5.模块化设计,其中的许多函数可以成为vhdl语言的通用经典例子(包含分频电路设计,动态扫描时钟设计,译码电路设计,存储器设计,存储回放显示设计)-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 1995 | Author: 方周 | Hits:

[VHDL-FPGA-Verilogbyvhdstopwatchl

Description: 1.高精度数字秒表(0.01秒的vhdl语言实现) 2.具有定时,暂停,按键随机存储,翻页回放功能; 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔,可控性高。 5.模块化设计,其中的许多函数可以成为vhdl语言的通用经典例子(包含分频电路设计,动态扫描时钟设计,译码电路设计,存储器设计,存储回放显示设计)-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 2048 | Author: 方周 | Hits:

[Otherdef1

Description: 实现D触发器的基本功能,D触发器的功能是时钟信号为上升沿时检测输入信号并将其赋值给输出信号并维持到下一个上升沿(压缩包内为所有MAXPLUS2程序)-The realization of the basic functions of D flip-flop, D flip-flop function is when the clock signal for the rising edge detection of input signal and its assignment to the output signal and to maintain until the next rising edge (compressed package MAXPLUS2 for all procedures)
Platform: | Size: 11264 | Author: 刘美 | Hits:

[VHDL-FPGA-Verilogclock

Description: XLINX做的数字钟,可以准确计时的。 用计数器和触发器实现。-XLINX do digital clock can be accurately timed. With counters and flip-flops to achieve.
Platform: | Size: 1007616 | Author: zhuning | Hits:

[Embeded-SCM Develop74LS90

Description: 学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-Learning digital circuits in the basic RS flip-flops, monostable multivibrator, clock generator and counting, decoding display unit integrated circuit applications.
Platform: | Size: 219136 | Author: 陈竺 | Hits:

[Othersheji2

Description: 一个秒表的硬件设计,学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applications.
Platform: | Size: 131072 | Author: 周妮 | Hits:

[VHDL-FPGA-Verilogd-flip

Description: 同步复位的D 触发器,该触发器有一个数据输入端D,时钟输入端CLK,清 零输入端CLR,数据输出端Q。CLR为1时,触发器复位-Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
Platform: | Size: 6144 | Author: wangminpeng | Hits:

[VHDL-FPGA-VerilogVerilogexample

Description: verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator-verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6 . The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator ....
Platform: | Size: 30720 | Author: vkiy | Hits:

[Embeded-SCM Developmain

Description: 1664双色点阵屏的翻页钟程序,欢迎大家下载,谢谢诶!-1664 two-color dot-matrix screen flip clock program, are welcome to download, thank you ah!
Platform: | Size: 7168 | Author: zhang | Hits:

[Documentsshuzi

Description: 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时,显示满刻度为23时59分59秒,并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源,采用低功耗的芯片及液晶显示器,发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74,计数器采用同步双十进制计数器74LS160,锁存译码器是74LS248,整电报时电路用74LS74,74LS32及扬声器构成。-Design a digital circuit, on the hours, minutes, seconds. Figures show that the timing device, 24-hour period, indicating full scale is 23:59:59 and the time with school functions and timekeeping functions of digital electronic clock. Scale integrated circuits used in the main circuit. The design of this system by the pulse logic circuit module, clock module, the clock display circuit decoding module, when the entire cable module, the campus module components. Using a battery powered, low-power chips and liquid crystal display generator using a quartz crystal oscillator, count of CD4060 oscillator and two D flip-flop 74LS74, two-decimal counter synchronous counter 74LS160, latch decoder is the 74LS248, the whole When telegraph circuits 74LS74, 74LS32 and loudspeaker
Platform: | Size: 449536 | Author: 张龙 | Hits:

[SCMLED_MATRIX_CLOCK_51

Description: 16*64LED点阵屏翻页钟,超强万年历-16* 64LED lattice screen flip clock, super calendar
Platform: | Size: 111616 | Author: zhuyi | Hits:

[VHDL-FPGA-Verilogsynchronization-clock-generation

Description: 引入了D 触发器的长帧同步时钟的产生,其是一个时钟分频的例子,特别提醒了如何在程序中引入触发器,适合初学者引用。-The introduction of the D flip-flop of long frame synchronization clock generation, it is an example of a clock divider, remind how the introduction of the program Trigger reference for beginners.
Platform: | Size: 190464 | Author: 快乐天使 | Hits:

[SCMclock

Description: This using Keil uVision 3 and Atmel Flip 3.4.3 The code is tested using 8051 microprocessor chip. 1) Copy and paste the attached code to Keil uVision. 2) Use the link below to configure in Keil for the 8051 chip. download here: https://www.keil.com/demo/eval/c51.htm Configuration: http://c8051.leongkj.net/short_courses/uvision3.htm 3)Use Atemel Flip 3.4.3 to export the code to the microprocessor. download link: http://www.atmel.com/tools/FLIP.aspx Open Atmel and click USB debug then once attached, click on USB and check BULB before importing to microprocessor. Once done, Uncheck BULB.-This is using Keil uVision 3 and Atmel Flip 3.4.3 The code is tested using 8051 microprocessor chip. 1) Copy and paste the attached code to Keil uVision. 2) Use the link below to configure in Keil for the 8051 chip. download here: https://www.keil.com/demo/eval/c51.htm Configuration: http://c8051.leongkj.net/short_courses/uvision3.htm 3)Use Atemel Flip 3.4.3 to export the code to the microprocessor. download link: http://www.atmel.com/tools/FLIP.aspx Open Atmel and click USB debug then once attached, click on USB and check BULB before importing to microprocessor. Once done, Uncheck BULB.
Platform: | Size: 1024 | Author: mdisam | Hits:

[SCMfanyeshizhong

Description: 16X64 强大的翻页时钟程序,时间,温度,补偿,多路闹铃控制,流动显示等等。-16X64 flip clock, time, temperature compensation, multiple alarm control, flow visualization, etc.
Platform: | Size: 203776 | Author: 杨新 | Hits:

[Picture Viewer10ge-jquery-tu-pian-xiao-guo

Description: 10个jquery实现的漂亮图片效果: 迅卖商城图片切换显示 jquery实现 jQuery简单的图片切换效果 jquery图片滚动切换插件 jquery图片切换滑动效果 jquery图片切换效果 jquery和CSS3定义的图片展示效果 动画组合画廊 jQuery和CSS3定义的全屏图片展示效果SIDEWAYS jQuery时钟翻页时钟效果 jquery 图片展示效果 jquery 图片画廊效果-10 jquery to achieve beautiful image effects: fast sell store pictures switch the display the jquery jQuery simple picture transition effects jQuery picture scroll switching the plugin jquery Photos switching sliding effect jQuery image transition effect jQuery and CSS3 defined picture showing the effect of animated portfolio gallery jQuery and CSS3 definition of full-screen images show the effect of Sideways jQuery clock flip clock effect jquery picture showing the effect of jquery Photo gallery effect
Platform: | Size: 4424704 | Author: | Hits:

[Other16X64shizhong

Description: 16X64单红翻页时钟程序调试成功,请放心使用,修改端口后即可使用-16X64 single red flip clock program debugging success, ease of use, can be used to modify the port after
Platform: | Size: 76800 | Author: 罗伟华 | Hits:

[Othershusefayeshizhong

Description: 双色翻页时钟程序调试成功,修噶端口即可使用,接口简单,用DS1302和DS18B20传感器实现-Color flip clock program debugging success, repair Karma port to use, simple interface with DS1302 and DS18B20 sensors to achieve
Platform: | Size: 52224 | Author: 罗伟华 | Hits:

[VHDL-FPGA-VerilogD-type-flip-flop

Description: 设计一个D型触发器,输入CK(时钟信号, ↑表示上升沿时刻),D(数据),Clear端(“0”时清零),输出Q-Design of a D-type flip-flop, the input CK (clock signal, ↑ indicates rising time), D (data), Clear end (" 0" is cleared), the output Q
Platform: | Size: 3072 | Author: 许光达 | Hits:

[JSP/JavaAndroid-moji-weather

Description: 本项目是一个仿照墨迹天气的桌面小插件例子源码,高仿墨迹天气桌面组件,可以实现翻页时钟和根据解析中国天气网天气更新天气和显示对应的天气图片,优化桌面插件居中、更新服务被系统干掉后会自动重启、判断手机网络是否连接等...注意安装以后桌面没有任何图标,只能在添加桌面小工具的时候看到)项目编码GBK默认编译版本2-The project is modeled on a desktop ink weather widget source code examples, high imitation ink weather desktop components, can achieve flip clock and updated weather and display the corresponding weather picture based on analysis of the Chinese weather network weather, optimize desktop plug-centered, update service is the system will automatically restart after the kill, it is determined whether the mobile network connection, etc ... Note the desktop after installation without any icon, only in time to add a desktop gadget to see) Item coding GBK default compiler version 2.3.3
Platform: | Size: 3180544 | Author: 周宇峰 | Hits:

[androidApptest

Description: 仿照墨迹天气的桌面小插件例子源码,高仿墨迹天气桌面组件,可以实现翻页时钟和根据解析中国天气网天气更新天气和显示对应的天气图片-Source desktop widget example modeled on the ink weather, high imitation ink weather desktop components, can flip clock and analytical China Weather Network Weather and weather updates to display the corresponding picture according to the weather
Platform: | Size: 3095552 | Author: zhchwl | Hits:
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