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[VHDL-FPGA-Verilog] frequency_counter_2(successful)(top-down design).r

Description: 小巧的频率计数器，VHDL源代码和仿真文件具全，直接从管工程文件拷贝过来。绝对可用。-compact frequency counters, VHDL source code and simulation with all documents directly from the control engineering documents copied. Absolutely available.
Platform: | Size: 126976 | Author: wl | Hits:

[Communication-Mobile] Viterbi

Description: 卷积码（2，1，6），完整的工程文件，已经调试通过-Convolutional code (2,1,6), complete engineering documents have been debugging through
Platform: | Size: 47104 | Author: jishanyi | Hits:

[VHDL-FPGA-Verilog] 200710122171387979

Description: 此源码为线性相位滤波的vhdl源码和设计心得体会，理论分析和工程实践总结相结合，有很大的参考价值-This source for the linear phase filter VHDL source code and design experiences, theoretical analysis and summary of the combination of engineering practice, has a great reference value
Platform: | Size: 737280 | Author: 骆军 | Hits:

[VHDL-FPGA-Verilog] design

Description: 华大机顶盒源码，包括所有源代码，还有详细的说明文档，不可多得实际工程，现已流片生产-Mandarin source set-top boxes, including all source code, as well as detailed documentation, rare practical engineering, is now streaming film production
Platform: | Size: 418816 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilog] crc

Description: 可以直接用于工程应用的crc校验VHDL编码 里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications
Platform: | Size: 90112 | Author: 毋杰 | Hits:

[VHDL-FPGA-Verilog] Uart_Send

Description: UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
Platform: | Size: 4096 | Author: wanyou2345 | Hits:

[VHDL-FPGA-Verilog] Quartus2_VerilogRoutine

Description: 该文档是基于QUARTUS2_6.0的Verilog试验例程，其中附有工程源码，对于初学者是最好的例程！它是本人花费一年多自学后写的例程，以便初学者入门，里面附有很多图解，很详细！-The document is based on the Verilog test QUARTUS2_6.0 routines, including an engineering source code, for beginners is the best routine! It is, I spent more than a year after self-written routines in order to beginners entry, which accompanied by many diagrams, very detailed!
Platform: | Size: 4041728 | Author: 王斌 | Hits:

[VHDL-FPGA-Verilog] pocp

Description: 简单的i/O接口的vhdl设计，包括工程，源码，仿真波形，为POC型的接口-Simple i/O interface of the VHDL design, including engineering, source code, simulation waveforms, for the POC-based interface
Platform: | Size: 204800 | Author: jiangliping | Hits:

[VHDL-FPGA-Verilog] FPEGVHDL

Description: 这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了-This is my study at FPEG/VHDL Express entry and improve engineering practice when the book written by one of the relevant code. However hard I organize out ah. Hope to have helped the U.S. ... ...
Platform: | Size: 3072 | Author: Zachary | Hits:

[VHDL-FPGA-Verilog] lab1_VHDL

Description: VHDL数字系统设计工程实践，包含实验的原理，真值表和结构图描述，以及相关的VHDL代码。-VHDL digital system design engineering practice, including the principle of the experiment, truth table and chart descriptions, and associated VHDL code.
Platform: | Size: 53248 | Author: wangfeijum | Hits:

[Com Port] RS485

Description: c8051f040单片机做的485通信源代码，适合工程。-c8051f040 microcontroller 485 to do the source code, for engineering.
Platform: | Size: 176128 | Author: yang | Hits:

[VHDL-FPGA-Verilog] FPGA_Book_cd

Description: 《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。-" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of this book is still very rich, involved in all aspects of the field of wireless communications. But for some relatively new technology, some of its FPGA implementation is too brief, it is difficult in practical engineering.
Platform: | Size: 1513472 | Author: 呙涛 | Hits:

[VHDL-FPGA-Verilog] encoderdecoder

Description: this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 142336 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] multiplexersemultiplexer

Description: this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 91136 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] srandDflipflop

Description: this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 205824 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] addersandsubtractors

Description: this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 65536 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] binarytograyandgraytobinarycodeconverter

Description: this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 61440 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] vga1012

Description: VHDL实现VGA显示的横竖彩条，可以进行横彩条，竖彩条的显示控制，包括源码和全部工程文件-VHDL achieve horizontal and vertical color VGA display article can be horizontal color bars, vertical color bars display control, including source code and all engineering documents
Platform: | Size: 492544 | Author: jacob | Hits:

[VHDL-FPGA-Verilog] uart-

Description: 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
Platform: | Size: 30720 | Author: mike | Hits:

[VHDL-FPGA-Verilog] VHDL-CODE

Description: 书籍源代码_基于Altera FPGA/CPLD的电子系统设计及工程实践 -Books source code _ of Altera FPGA/CPLD-based electronic system design and engineering practice
Platform: | Size: 30523392 | Author: 汪晨 | Hits:
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