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Description: 一种基于FPGA实现的FFT结构
调从基本元器件开始的计算机硬件系统的设计与实现,大多设置在自动控制系,形成了与应用系统结合的计算机教育。 1966年多处理器平台FPGA 学习目标 (1) 理解为什么嵌入式系统使用多处理器 (2) 指出处理器中CPU和硬件逻辑的折衷 -FPGA-based FFT realize the structure of the tune from the beginning of the basic components of computer hardware system design and implementation, most of them located in the Automatic Control Department, formed a combination and application of computer education system. 1966 multi-processor FPGA platform for learning goals (1) to understand why the use of multi-processor embedded system (2) pointed out that the processor CPU and the hardware logic of compromise
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Size: 109568 |
Author: 陈松 |
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Description: 适用于MP3音乐中波形处理（FFT算法），该代码采样不是很多，更适合嵌入式产品中MP3播放器波形处理-MP3 music for waveform processing (FFT algorithm), the code is not a lot of sampling, it is more suitable for embedded products MP3 player waveform handle
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Size: 48128 |
Author: 风笛 |
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Description: 嵌入式系统中FFT算法研究,看看对要使用VC++进行数字信号处理的朋友还是很实用的-FFT algorithm for embedded systems research, to be used to see on VC++ For digital signal processing of a friend or a very practical
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Size: 787456 |
Author: 陈刚毅 |
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Description: 嵌入式系统中FFT算法研究,看看对要使用VC++进行数字信号处理的朋友还是很实用的-FFT algorithm for embedded systems research, to be used to see on VC++ For digital signal processing of a friend or a very practical
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Size: 9216 |
Author: 陈刚毅 |
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Description: C语言实现的fft蝶形运算，是个通用程序，移植一下即可使用在其他嵌入式芯片上-C language implementation of the fft butterfly is a common procedure, transplant what can be used in other embedded chip
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Size: 21504 |
Author: liu yang |
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Description: Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved
FFT algorithm. The whole FFT structure was implemented based on self-designed
modules and by manipulating the embedded Virtex II FPGA’s modules. The
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Size: 1514496 |
Author: nikhil |
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Description: 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,实现了基于FFT的音频信号分析-Altera Cyclone II FPGA family based embedded high-performance embedded IP core (Nios) soft core processor to achieve a FFT-based audio signal analysis
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Size: 2048 |
Author: 季云 |
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Description: 利用Altera的IP核，实现FFT算法使用信息流模式读写，使用SignalTap II嵌入式逻辑分析仪观察信号，A/D只要是并行的8位芯片都可以。-Achiving FFT by using Altera IP Core,you can observe the signal by the embedded logic analyzer Signal Tap II,as for A/D device, it s suitable for a parllarel 8 bits A/D device.
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Size: 22096896 |
Author: 常泽文 |
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