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[SourceCodeeetop.cn_at91sam9xd_DDR

Description:
Platform: | Size: 23618 | Author: bobcat321 | Hits:

[VHDL-FPGA-Verilogmodelsim_6.3f_6.4b_6.5_crck

Description: 目前这个生成的key在modelsim se 6.3f 6.4b 6.5测试没问题。因为这几个版本是我逐步升级的,应该说从6.3f~6.5的都可以用。测试环境为windows xp sp3. vista没有测试。按理说是一样的。使用过程中遇到的一些问题的解决办法关于key里面生成中文字符的情况产生原因是,windows当前用户名和主机名是中文,修改之后重新生成一次。在安装的时候要设置环境变量LM_LICENSE_FILE,指向lincense的的路径和文件名。需要在cmd下使用modelsim的命令,需要将modelsim的win32目录添加到环境变量path中,这些都是EDA软件安装的一些基本常识了。对于modelsim的较新版本,会有提示。但是还要设置LM_LICENSE_FILE。 关于网卡号的设置可以使用-h的参数,更多参数请在命令行下使用-help来查看。 2009年9月14日测试支持最新的6.5C-modelsim se 6.3f 6.4b 6.5
Platform: | Size: 308224 | Author: yanghong | Hits:

[Othereetop.cn_Video_Demystified1

Description: Video Demystified部分翻译-Video Demystified partially translated
Platform: | Size: 416768 | Author: David Lin | Hits:

[Communication-Mobileeetop[1].cn_channelcoding

Description: 卷积码的维特比译码Matlab仿真,十分好用-eetop[1].cn_Convolutional-Encoder-Viterbi.zip
Platform: | Size: 945152 | Author: sunkai | Hits:

[Othereetop.cn_6_72

Description: mpeg1-mpeg4标准的中文版文档,非常的详细 深入,有实例-mpeg1-mpeg4 standard Chinese version of the document, very thorough, there are examples of
Platform: | Size: 5021696 | Author: magicyang | Hits:

[VHDL-FPGA-Verilogeetop.cn_digital_clock

Description: 基于VHDL的数字时钟设计课件,简单,实用-VHDL-based Digital Clock Design Courseware
Platform: | Size: 271360 | Author: 孤独剑 | Hits:

[matlabeetop.cn_Simulink

Description: simulink简明教程,初步了解simulink的使用方式-simulink simple tutorial a preliminary understanding of the usage simulink
Platform: | Size: 1093632 | Author: 马萍 | Hits:

[Othereetop.cn_subtitling

Description: subtitles标准文件,原版标准文件,包括两个文件:A009.PDF和Ets300743_e1.pdf-subtitles
Platform: | Size: 254976 | Author: 林子 | Hits:

[Othereetop.cn_

Description: _有源滤波器精确设计手册详细介绍了各种有源滤波器设计-_ Active Filter Design Manual precise details of the various active filter design
Platform: | Size: 3246080 | Author: 别问 | Hits:

[VHDL-FPGA-VerilogispLEVER

Description: eetop.cn_ispLEVER培训教程FPGA设计流程.rar
Platform: | Size: 648192 | Author: zmq | Hits:

[Othereetop.cn_Simulink3

Description: matlab中simulink比较详细的介绍,看完可以学习到两种实现simulink的方法。-matlab in a more detailed description simulink, two kinds of reading can learn to achieve simulink methods.
Platform: | Size: 194560 | Author: 小姚 | Hits:

[Othereetop[1].cn_ise_book

Description: Xilinx ISE 9.x fpga&cpld设计指南 光盘附带内容
Platform: | Size: 3807232 | Author: 罗德文 | Hits:

[matlabeetop.cn_HCS300

Description: HCS300编码。。还要最少20个字?够了吧-HCS300 code. . But also at least 20 words? Enough, right? ?
Platform: | Size: 38912 | Author: 王明明 | Hits:

[VHDL-FPGA-Verilogeetop.cn_Altera6.0_10.0sp1

Description: eetop.cn_Altera破解器6.0-10.0sp1.rar包括最新的Quartus10.0破解版。-eetop.cn_Altera cracker 6.0-10.0sp1.rar including the latest Quartus10.0 cracked version.
Platform: | Size: 400384 | Author: lijiang | Hits:

[Linux-Unixeetop.cn_Calibre_zhongwen

Description: linux calibre 介绍,很详细,适合初学者。-linux calibre
Platform: | Size: 624640 | Author: 王振 | Hits:

[Othereetop

Description: 相信很多人为了eetop的信元发愁吧 这个简单的灌水机用于在eetop灌水区灌水 在运行脚本前,先让IE记住你的账号密码。然后就双击等待成为大富翁吧-This is a perl script used to automatically earn xinyuan of eetop. Let IE remember your account and password before run this script.
Platform: | Size: 1024 | Author: Wang Kun | Hits:

[VHDL-FPGA-Verilogeetop.cn_Crack_Modelsim.SE.6.6

Description: Modelsim 6.6c keygen
Platform: | Size: 667648 | Author: 王京 | Hits:

[VHDL-FPGA-Verilogeetop.cn_licgen_ise_13.1

Description: this the license genarator for xilinx ISE DESIGN SUIT 13.1 -this is the license genarator for xilinx ISE DESIGN SUIT 13.1
Platform: | Size: 292864 | Author: raghul | Hits:

[Othereetop.cn_2440boot

Description: eetop上边的boot很有参考价值哦,,可以用来学习参考-eetop top of the boot Oh great reference value, can be used to study reference
Platform: | Size: 406528 | Author: hongxiao | Hits:

[Embeded-SCM Developeetop.cn_STM8函数库中文参考

Description: eetop.cn_STM8函数库中文参考(eetop.cn_STM8 function library)
Platform: | Size: 99328 | Author: BBB1BB | Hits:
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