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[Other resource] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input / Solution Series (ISERDES) and serial output / Solution Series (O Legacy) function.
Platform: | Size: 297475 | Author: mingming | Hits:

[Other] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series (ISERDES) and serial output/Solution Series (O Legacy) function.
Platform: | Size: 296960 | Author: mingming | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[Embeded-SCM Develop] ddr_ddr2_sdram

Description: 基于NIOS II的ddr2控制器,配有详细的文档,经验证后可使用.-NIOS II based on the DDR2 controller, equipped with detailed documentation, the experience can be used after certification.
Platform: | Size: 3486720 | Author: Jackie | Hits:

[VHDL-FPGA-Verilog] 1189152740

Description: DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve
Platform: | Size: 84992 | Author: 白皓 | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] c_xapp858

Description: 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the interface used to achieve high-performance DDR2 SDRAM controller and data acquisition technology. This data collection technique used in each Virtex ™ -5 I/O has an input serializer/deserializer (ISERDES) and output double data rate (ODDR) function.
Platform: | Size: 447488 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Platform: | Size: 209920 | Author: guoxiaojin | Hits:

[Software Engineering] DDR2deFPGAsheji

Description: 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
Platform: | Size: 2525184 | Author: 张桃源 | Hits:

[VHDL-FPGA-Verilog] the_design_and_realization_of_DDR2-SDRAM_controlle

Description: ddr2控制器的设计与实现,详细介绍了其结构和思想-the design and realization of DDR2-SDRAM controller
Platform: | Size: 646144 | Author: alins | Hits:

[VHDL-FPGA-Verilog] ddr2_sdram_latest[1].tar

Description: ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
Platform: | Size: 1779712 | Author: hxr | Hits:

[SCM] ug_ddr_sdram

Description: DDR and DDR2 SDRAM Controller Compiler 的用户向导-DDR and DDR2 SDRAM Controller Compiler User Guide
Platform: | Size: 1005568 | Author: xl | Hits:

[Software Engineering] byNeyno_

Description: micron data sheet for designing the ddr2 sdram controller part1
Platform: | Size: 16384 | Author: ravi kishore | Hits:

[Software Engineering] childers

Description: micron data sheet for designing the ddr2 sdram controller part2
Platform: | Size: 1118208 | Author: ravi kishore | Hits:

[Software Engineering] sdram_controller_latest.tar

Description: This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board
Platform: | Size: 29696 | Author: sakthivel | Hits:

[VHDL-FPGA-Verilog] ddr2_v5

Description: 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
Platform: | Size: 13487104 | Author: 铁鹏涛 | Hits:

[VHDL-FPGA-Verilog] test_ddr2_ip

Description: ddr2 SDRAM 高性能控制器及测试-DDR2 SDRAM High Performance Controller
Platform: | Size: 11807744 | Author: zdwang | Hits:

[Technology Management] DDR3-User-Guide

Description: 在DDR3内存控制器一起使用JESD79-3C符合标准SDRAM器件接口。内存类型，如DDR1 SDRAM，DDR2 SDRAM，SDR SDRAM，SBSRAM和异步不支持的回忆。在DDR3内存控制器，SDRAM，可用于程序和数据存储。梯形失真校正设备有一个实例。-Use JESD79-3C standard SDRAM DDR3 memory controller interface devices together. Memory types, such as DDR1 SDRAM, DDR2 SDRAM, SDR SDRAM, SBSRAM and do not support asynchronous memories. In DDR3 memory controller, SDRAM, can be used for program and data storage. Keystone device has one instance.
Platform: | Size: 479232 | Author: youwenjiang | Hits:

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