avnet_notice_2008.txt
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
.....................................\datasheet.txt
.....................................\ddr2_32mx32.bit
.....................................\log.txt
.....................................\mig.prj
.....................................\par
.....................................\...\create_ise.bat
.....................................\...\ddr2_32Mx32.cdc
.....................................\...\ddr2_32Mx32.ucf
.....................................\...\ddr2_32Mx32_user_interface.cpj
.....................................\...\ddr2_speedway.bat
.....................................\...\ddr2_speedway.ise
.....................................\...\ddr2_speedway.ise_ISE_Backup
.....................................\...\ise_flow.bat
.....................................\...\ise_run.txt
.....................................\...\readme.txt
.....................................\...\set_ise_prop.txt
.....................................\rtl
.....................................\...\ddr2_32Mx32.v
.....................................\...\ddr2_32Mx32_addr_gen_0.v
.....................................\...\ddr2_32Mx32_cal_ctl_0.v
.....................................\...\ddr2_32Mx32_cal_top.v
.....................................\...\ddr2_32Mx32_clk_dcm.v
.....................................\...\ddr2_32Mx32_cmd_fsm_0.v
.....................................\...\ddr2_32Mx32_cmp_data_0.v
.....................................\...\ddr2_32Mx32_controller_0.v
.....................................\...\ddr2_32Mx32_controller_iobs_0.v
.....................................\...\ddr2_32Mx32_data_counter_0.v
.....................................\...\ddr2_32Mx32_data_path_0.v
.....................................\...\ddr2_32Mx32_data_path_iobs_0.v
.....................................\...\ddr2_32Mx32_data_read_0.v
.....................................\...\ddr2_32Mx32_data_read_controller_0.v
.....................................\...\ddr2_32Mx32_data_write_0.v
.....................................\...\ddr2_32Mx32_dqs_delay.v
.....................................\...\ddr2_32Mx32_fifo_0_wr_en_0.v
.....................................\...\ddr2_32Mx32_fifo_1_wr_en_0.v
.....................................\...\ddr2_32Mx32_infrastructure.v
.....................................\...\ddr2_32Mx32_infrastructure_iobs_0.v
.....................................\...\ddr2_32Mx32_infrastructure_top_0.v
.....................................\...\ddr2_32Mx32_iobs_0.v
.....................................\...\ddr2_32Mx32_main_0.v
.....................................\...\ddr2_32Mx32_parameters_0.v
.....................................\...\ddr2_32Mx32_ram8d_0.v
.....................................\...\ddr2_32Mx32_rd_gray_cntr.v
.....................................\...\ddr2_32Mx32_s3_dm_iob_0.v
.....................................\...\ddr2_32Mx32_s3_dqs_iob.v
.....................................\...\ddr2_32Mx32_s3_dq_iob.v
.....................................\...\ddr2_32Mx32_tap_dly.v
.....................................\...\ddr2_32Mx32_top_0.v
.....................................\...\ddr2_32Mx32_user_logic_0.v
.....................................\...\ddr2_32Mx32_wr_gray_cntr.v
.....................................\sim
.....................................\...\ddr2_model.v
.....................................\...\ddr2_model_parameters.vh
.....................................\...\glbl.v
.....................................\...\sim.do
.....................................\...\sim.exe
.....................................\...\simulation_help.chm
.....................................\...\sim_tb_top.v
.....................................\synth
.....................................\.....\ddr2_32Mx32.lso
.....................................\.....\ddr2_32Mx32.prj
.....................................\.....\ddr2_32Mx32.sdc
.....................................\.....\mem_interface_top.xcf
.....................................\.....\mem_interface_top_synp.sdc
.....................................\.....\script_synp.tc