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[Other resource] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347004 | Author: Hubert | Hits:

[Other] u26a_spice

Description: ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
Platform: | Size: 297984 | Author: | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0

Description: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Platform: | Size: 1688576 | Author: li ji wei | Hits:

[VHDL-FPGA-Verilog] vga_control

Description: vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
Platform: | Size: 1024 | Author: zys | Hits:

[VHDL-FPGA-Verilog] DDR2Controller

Description: DDR2 Controller DDR2 Controller
Platform: | Size: 312320 | Author: tg | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] ddr2

Description: 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Platform: | Size: 2793472 | Author: Zhao Bill | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Platform: | Size: 209920 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] DDR2_controller

Description: DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
Platform: | Size: 1818624 | Author: alins | Hits:

[VHDL-FPGA-Verilog] ddr2_test

Description: 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
Platform: | Size: 10875904 | Author: 左洪成 | Hits:

[VHDL-FPGA-Verilog] DDR2_Memory_Test

Description: DDR2 controller which contains verilog files，pdf and so on
Platform: | Size: 234496 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] DDRCHv11

Description: Source code for ddr2 dram controller for BEEE
Platform: | Size: 661504 | Author: shiva | Hits:

[VHDL-FPGA-Verilog] 2048Mb_ddr2_verilog_model

Description: ddr2 verilog model,用于验证DDR2 Controller。-DDR2 Verilog model, and used to verify the DDR2 Controller.
Platform: | Size: 2634752 | Author: 天空 | Hits:

[Software Engineering] VerilogHDL-DDR2SDRAM

Description: 关于DDR2 控制器的设计 是通过verilog语言设计-DDR2 controller design through verilog language design
Platform: | Size: 993280 | Author: 张雷岳 | Hits:

[Software Engineering] DDR2-controller

Description: My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor
Platform: | Size: 10240 | Author: thuanbk | Hits:

[VHDL-FPGA-Verilog] DDR2-verilog

Description: ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the FPGA and DDR2 communications.
Platform: | Size: 1490944 | Author: wei | Hits:

[Other] DDR2_Control

Description: 本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)
Platform: | Size: 13041664 | Author: chenpeiweiweiwei | Hits:
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