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Description: 这个程序可以直接从显示器读取ddc数据。支持ati显卡。可以随意修改。方便大家研究利用。-This procedure can be read directly from the display ddc data. Ati graphics card support. Can be modified. To facilitate research use.
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Size: 4179968 |
Author: 刘柱 |
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Description: 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR-DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
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Size: 2048 |
Author: yeong |
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Description: This GMS down upper converter and down converter in simulink. you may understand the structure in here, believe is useful to those who interested in telecommunication-This is GMS down upper converter and down converter in simulink
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Size: 232448 |
Author: Nelson Loh |
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Description: 数字下变频的Verilog程序，测试可以直接使用，将A/D信号下变频为基带I，Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
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Size: 3072 |
Author: gaigai |
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Description: simulink demo of ddc
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Size: 173056 |
Author: bnpvas |
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Description: CS8955控制TV软件。用MCU做模拟电视的控制。-CS8955+TV+TNJ7355(tuner).The CS8955 micro-controller is an 8051 CPU core
embedded device targeted for LCD Monitor, LCD TV,
Home Appliance, or Consumer Products application.
The CS8955 is pin-out compatible with MCS-51
family .MCU. It includes an 8051 CPU core, a 64K-byte
internal program Flash-ROM, a 512-byte SRAM, 6
channels of PWM DAC, and 4 channels of 6-bit ADC
(Analog to Digital Converter). It also includes a Boot-
Code-Free ISP (In System Programming), which
allows users to update the programming codes easily.
In addition, there are two IIC Slave B ports supporting
VESA DDC 2B/2Bi/2B+/CI standards for both D-sub
and DVI interfaces in LCD Monitor/TV application. An
external 64K bytes data flash memory can be
accessed by properly setting of Port 0, Port 2 and
Port 3.6/3.7.
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Size: 578560 |
Author: martinliao |
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Description: 这是一个用verilog HDL实现的实现数字下变频的源代码。-This is a verilog HDL used to achieve the realization of digital down conversion of the source code.
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Size: 2790400 |
Author: 王坤 |
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Description: 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
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Size: 1543168 |
Author: hcq |
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Description: 数字上下变频FPGA设计的详细介绍资料，还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
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Size: 357376 |
Author: 陈洁 |
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Description: 中频数字接收机设计与实现 对中频数字接收机方案的可行性作了分析，并通过系统仿真工具SystemView对A／D，数字下变频(DDC)及AM、FM等调制信号的软件解调作了仿真。-Design and implementation of a digital intermediate frequency receiver
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Size: 2051072 |
Author: ldd |
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