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[Other resource] crc_32_16

Description: crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
Platform: | Size: 297370 | Author: likj | Hits:

[VHDL-FPGA-Verilog] crc_16

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Platform: | Size: 31744 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] crc_32_16

Description: crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
Platform: | Size: 296960 | Author: likj | Hits:

[Crack Hack] crc

Description: 此源代码实现了CRC5和CRC16的校验以及校验码的产生，可以直接用于RFID标签数字电路。-This source code CRC5 and realize the CRC16 checksum and the emergence of parity-check codes, RFID tags can be directly used for digital circuits.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[SCM] CRC

Description: 循环冗余码校验（CRC）是一种可靠性很高的串行数据校验方法。介质循环冗余码校验的基本原理，并分别用单片机和CPLD作了循环冗余码验的软件实现和硬件实现。包括汇编语言和VHDL语言源程序-Cyclical redundancy check (CRC) is a high reliability of the serial data validation methods. Media cyclical redundancy check of the basic principles, and were made with MCU and CPLD Cyclic Redundancy Code inspection software and hardware realize realize. Including assembly language and VHDL language source
Platform: | Size: 14336 | Author: llhg | Hits:

[ELanguage] atm

Description: atm信元检测，CRC循环冗余码编码和校验-atm cell detection, CRC cyclical redundancy check code and
Platform: | Size: 80896 | Author: wh | Hits:

[VHDL-FPGA-Verilog] CRC

Description: verilog 实现循环冗余校验 源代码-Cyclic Redundancy Check realize Verilog source code
Platform: | Size: 367616 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] CRC_xapp562

Description: crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,
Platform: | Size: 49152 | Author: lh | Hits:

[VHDL-FPGA-Verilog] crc

Description: VHDL cyclic redundancy check generator und receiver
Platform: | Size: 4096 | Author: Digitalkurt | Hits:

[Crack Hack] crc

Description: CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project
Platform: | Size: 1024 | Author: fang | Hits:

[source in ebook] crcsend

Description: 用vhdl代码实现循环冗余检验，CRC即Cycic Redundancy Check-Vhdl code used to achieve the cycle redundancy check, CRC that Cycic Redundancy Check
Platform: | Size: 266240 | Author: songbinghui | Hits:

[Other] crc

Description: 循环冗余校验码CRC的VerilogHDL源程序-CRC cyclic redundancy check code of the source VerilogHDL
Platform: | Size: 1024 | Author: hh | Hits:

[matlab] RFC_1622_CRC16_m

Description: RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with script to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
Platform: | Size: 1024 | Author: spaander | Hits:

[VHDL-FPGA-Verilog] crc

Description: 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Platform: | Size: 436224 | Author: 虎 | Hits:

[Program doc] crc_explain

Description: 循环冗余校验 CRC 的算法分析和程序实现。通信的目的是要把信息及时可靠地传送给对方，因此要求一个通信系统传输消息必须可靠与快速，在数字通信系统中可靠与快速往往是一对矛盾。为了解决可靠性，通信系统都采用了差错控制。本文详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其算法实现-Cyclic Redundancy Check
Platform: | Size: 106496 | Author: 朱红 | Hits:

[VHDL-FPGA-Verilog] crc

Description: crc校验，是用于编码中的一种校验方法，这是书本中学习的方法-crc check is a check for the encoding method, which is the method book to learn
Platform: | Size: 4096 | Author: luozhiyuan | Hits:

[VHDL-FPGA-Verilog] hdlc_rs

Description: 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual process
Platform: | Size: 6144 | Author: 周宽裕 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC循环校验码的生成。文件里是（40，32）的校验码生成电路，采用串行输入、串行输出的方式。-CRC checksum generation cycle. File is (40,32) of the check code generation circuit, the use of serial input, serial output mode.
Platform: | Size: 143360 | Author: 李雪茹 | Hits:

[VHDL-FPGA-Verilog] crc

Description: 本代码是CRC循环冗余校验实例，包含顶层原理图文件，十分直观-The CRC is cyclic redundancy check code examples, including the top-level schematic file, very intuitive
Platform: | Size: 449536 | Author: renjiale | Hits:
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