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Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则
asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到
verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库
的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit -
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Size: 359836 |
Author: 任学 |
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Description: The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.
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Size: 9936060 |
Author: Jawen |
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Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE
第一章 Modelsim编译Xilinx库
第二章 调用Xilinx CORE-Generator
第三章 使用Synplify.Pro综合HDL和内核
第四章 综合后的项目执行
第五章 不同类型结构的仿真
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Size: 218238 |
Author: 青岚之风 |
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Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则
asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到
verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库
的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: |
Size: 359424 |
Author: 任学 |
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Description: The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification. -The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.
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Size: 9935872 |
Author: Jawen |
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Description: 一个VBS病毒生成器的核心代码，可以分析下VBS病毒-a VBS virus generator at the core code can be analyzed under the VBS virus
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Size: 6144 |
Author: 张式庭 |
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Description: 本系统基于反馈控制思想，由交直流转换电路、DC-DC变换器、步进电路模块和显示模块4个模块电路构成开关稳压电源。交直流转换电路整流部分采用全波桥式整流电路形式，DC-DC变换器以TL494有主核心设计并加上简单滤波电路及RC放电回路所构成的回路控制器。它能把脉冲宽度变化的信号转换成与脉冲宽度成正比变化的直流信号，进而实现闭环单回路控制。由单片机控制
数字定位器X9241的电阻,进而控制输出电压。显示模块由LCD1602构成。
-Based on feedback control of the system of thought, from AC-DC converter circuit, DC-DC converters, stepper circuit module and display module 4 module circuit switching power supply. AC-DC converter circuit using full-wave rectifier part of the circuit form of bridge rectifier, DC-DC converter to TL494 have the main core of the design and add a simple RC filter circuit and discharge circuit posed by the loop controller. It can change the pulse width signals into changes with the pulse width is proportional to the DC signal, and thus realize the closed-loop single-loop control. By the single-chip microcomputer to control the number of locator X9241 resistance, thereby control the output voltage. LCD1602 constituted by the display module.
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Size: 52224 |
Author: 苏永生 |
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Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE
第一章 Modelsim编译Xilinx库
第二章 调用Xilinx CORE-Generator
第三章 使用Synplify.Pro综合HDL和内核
第四章 综合后的项目执行
第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
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Size: 218112 |
Author: 青岚之风 |
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Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
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Size: 1589248 |
Author: joan |
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Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。
设计思路
根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。
-Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
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Size: 8192 |
Author: lijq |
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Description: 介绍了以DSP为核心的励磁控制系统,利用其事件管理器能直接输出PWM波的特点,通过对永磁同步发电机的运行参数的监测与处理,自动调节复合式励磁发电机的电励磁调节器,使其输出电压保持稳定.实验结果表明该控制器性能良好,实用性强.-Introduced to the DSP as the core excitation control system, event manager to use its direct output PWM wave characteristics of permanent magnet synchronous generators of the operating parameters of the monitoring and processing, automatic adjustment composite electrical excitation generator excitation regulator , and its output voltage to remain stable. The experimental results show that good performance of the controller, practical.
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Size: 601088 |
Author: 将建 |
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Description: 利用ISE的core generator生成的存储器接口设计（MIG），包括example design和user design-ISE using the core generator to generate the memory interface design (MIG), including the example design and user design
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Size: 951296 |
Author: 彭朋 |
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Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
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Size: 6144 |
Author: Jayesh |
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Description: Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro
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Size: 10615808 |
Author: rakesh |
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Description: Xilinx IP core 生成手册-Block_Memory_Generator
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Size: 1935360 |
Author: wang pu |
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Description: A easy simple for Xilinx Chipscope Pro, the example shows how to insert cores of VIO, ILA from core generator and verilog code.
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Size: 369664 |
Author: DANIEL PAN |
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Description: The design used in this tutorial is a hierarchical, HDL-based design. The top-level design
file is an HDL file that references several other lower-level macros. The lower-level macros
are either HDL modules or CORE Generator modules.
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Size: 394240 |
Author: SEEDSTART |
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Description: The design used in this tutorial is a hierarchical, HDL-based design. The top-level design
file is an HDL file that references several other lower-level macros. The lower-level macros
are either HDL modules or CORE Generator modules.
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Size: 756736 |
Author: SEEDSTART |
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Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于
ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用
Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
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Size: 4096 |
Author: |
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Description: mybatis-generator-core
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Size: 500736 |
Author: fweffe |
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