Description: The basic parts of the BFSK transmitter are the preamble and the data input circuit. The preamble sequence is positioned in front of each packet of 122 bits for a total of 128 bits packet. The main purpose of the preamble is to facilitate the reception, providing both bit and packet synchronization. The data input circuit mainly consists from memory elements and a convolutional encoder with r=1/2. Thus, the input bits must be stored in a temporary memory and be partitioned in blocks of 61 bits. Then the convolutional encoder doubles the bits and adds two more trail bits at the end of the message. A multiplexer makes sure that that the correct sequence, choosing between preamble and encoded bit, is propagating to the next stage. The next stage of the transmitter consists of two direct digital synthesizers (DDS), and a multiplexer that is fed with zeros and ones to choose between the two frequencies. For each bit, we allow 64 samples of the respective frequency to be transmitted. Although the implementation of the selection between the two frequencies is strait forward, the enable port of the multiplexer should be used along with a Matlab Code (MCode) block in order to prevent the propagation of some initial undefined states during initialization. The only functionality of the MCode block is to enable the multiplexer after the first bit of the preamble is detected. Finally, pulse shaping is not used and the addition of a single filter after the last multiplexer would suffice to implement this functionality. Platform: |
Size: 31381 |
Author:publicxz |
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Description: 卷积码是一种有记忆的编码，在任意给定的时间单元处，编码器的n个输出不仅与此时间单元的k个输入有关，而且也与前m个输入有关。卷积码通常表示为：（n,k,m）
本次仿真采用（2，1，3）卷积码。
-convolutional code is a kind of code memory, in any given unit of time, the encoder output n this time not only with the elements of the k input, but also with the input m. Convolutional codes are usually stated as : (n, k, m), the simulation used (2,1,3) convolutional code. Platform: |
Size: 3072 |
Author:yx |
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Description: This program includes:
[5 7] convolutional code (encoder) + BPSK + AWGN + MAP (decoder). It evaluates Bit Error Rate and plots it versus SNR(signal to Noise Ratio).
-This program includes:
[5 7] convolutional code (encoder)+ BPSK+ AWGN+ MAP (decoder). It evaluates Bit Error Rate and plots it versus SNR(signal to Noise Ratio).
Platform: |
Size: 1024 |
Author:阳关 |
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Description: 强烈推荐好用的卷积码编码，维特比译码和软判决，本代码简易可行。-Strongly recommend use of the convolutional code encoder, Viterbi decoder and soft decision, the code simple and feasible. Platform: |
Size: 3072 |
Author:胡卓 |
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Description: simulating a convolutional encoder
allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate Platform: |
Size: 1024 |
Author:郑中 |
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Description: Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。-Generate trellis data of a rate-1/n convolutional encoder. Convolutional codes 1/n of the encoder, the attention generated by the non-system code. Platform: |
Size: 4096 |
Author:戈津生 |
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Description: Viterbi decoder for nonsystematic convolutional code. The encoder could be designed arbitrary through the generate matrix and parameter k. The number of row of generate matrix is output bits, and collom is constraint length. Parameter k is the number of parallel input. test.m is the main file. Platform: |
Size: 3072 |
Author:studenter |
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Description: Its a convolutional encoder with code rate of 1/2 and constraint length of 3.
i/p=1 bit
o/p=2 bits with 4 memory elements Platform: |
Size: 480256 |
Author:Adnan |
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Description: 实现卷积编码和相应的维特比译码（卷积码编码器为（2，1，3），维特比译码针对第1、3位模二加和第1、2位模二加）-Convolutional coding and the corresponding realization of Viterbi decoding (convolutional code encoder for the (2,1,3), Viterbi decoder bit mode for the first 1,3 and 1,2 position two plus two plus model ) Platform: |
Size: 2048 |
Author:张程 |
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Description: 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by contrast matlab and modelsim simulation results validate the design. Platform: |
Size: 19602432 |
Author:郭婷 |
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Description: 在MATLAB上设计一个（2，1，3）卷积编码器和对应的采用维特比译码算法的译码器。编码器的生成多项式为：[1 0 1；1 1 1]。将编码器的输出经过一个高斯白噪声信道的结果作为译码器的输入，观察比较译码器输出和编码器输入，了解卷积码的容错性，并计算译码结果的误比特率.(A convolutional coder (2, 1, 3) and corresponding decoder using Vitby decoding algorithm are designed on MATLAB. The generating polynomial of encoder is: [1 01; 11 1]. The output of the encoder through a Gauss white noise channel as a result of the decoder input, compare the output of the decoder and encoder input, understand the fault tolerance of convolutional code, and calculate the decoding results of bit error rate.) Platform: |
Size: 5120 |
Author:semperqaq
|
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