Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - clock xilinx

Search list

[Other resource] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过
Platform: | Size: 327663 | Author: lg | Hits:

[Communication] clock

Description: verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，
Platform: | Size: 10133 | Author: 王忠 | Hits:

[SCM] 7seg_led

Description: 使用xilinx公司的FPGA实现了七段码的定时器时钟程序-use of the Xilinx FPGA in paragraph 107 of the Code timer clock procedures
Platform: | Size: 222208 | Author: 张天齐 | Hits:

[VHDL-FPGA-Verilog] clockbyvhdl

Description: 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
Platform: | Size: 27648 | Author: 马永涛 | Hits:

[Technology Management] 06626_DLL

Description: XILINX的DLL的使用介绍，对于时钟的应用有很大的帮助-XILINX the use of the DLL, the application for the clock will be very helpful
Platform: | Size: 1009664 | Author: fei0318 | Hits:

[VHDL-FPGA-Verilog] ClockDiv

Description: 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
Platform: | Size: 774144 | Author: 刘小军 | Hits:

[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[Other] hdb3_proc

Description: HDB3编解码，含时钟提取，极高的效率和可靠性，VHDL。-HDB3 coding and decoding, including clock extraction, high efficiency and reliability, VHDL.
Platform: | Size: 4096 | Author: BrivaMa | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] eternityclock

Description: 一个在Xilinx spartan3实现的时钟，具有时分秒的计时显示以及年月日的显示，很有参考价值-A Xilinx spartan3 realize the clock, with time-accurate time display and date display, a good reference
Platform: | Size: 773120 | Author: Roger | Hits:

[Program doc] clock

Description: verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered
Platform: | Size: 10240 | Author: 王忠 | Hits:

[MPI] v2_fifo_vhd_258

Description: 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。-This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Platform: | Size: 92160 | Author: muerqing | Hits:

[VHDL-FPGA-Verilog] clock_module_ref

Description: Xilinx clock module design
Platform: | Size: 2048 | Author: Mingli | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[VHDL-FPGA-Verilog] Xilinx_DCM

Description: 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Platform: | Size: 8192 | Author: ise_dcm | Hits:

[VHDL-FPGA-Verilog] clock

Description: clock example for xilinx spartan 3 starter board-clock example for xilinx spartan 3 starter board....
Platform: | Size: 401408 | Author: hiren vadalia | Hits:

[VHDL-FPGA-Verilog] clock

Description: XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the development environment that can be selected to VHDL, the other is verilog, huh, huh. Hope that we can really spend, very good " based on ISE' s Clock"
Platform: | Size: 2779136 | Author: 江源 | Hits:

[VHDL-FPGA-Verilog] dcm

Description: Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
Platform: | Size: 1263616 | Author: 许磊 | Hits:

[VHDL-FPGA-Verilog] digital-clock

Description: Digital clock applicatian using seven segment with fpga xilinx
Platform: | Size: 2048 | Author: Ali Riza Simsek | Hits:
« 12 3 4 5 »

CodeBus www.codebus.net