Search - clk verilog

[VHDL-FPGA-Verilog] pcm

Description: 该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
Platform: | Size: 8192 | Author: 许嘉璐 | Hits:

[VHDL-FPGA-Verilog] 8LEDverilog

Description: //led.v /*------------------------------------- LED显示模块：led(CLK,AF,ADDR,DATA) 功能：显示注意事项： 8位LED 参数： CLK:扫妙时钟输入，推荐1kHz AF:数码管输出，a～h ADDR:数码管选择位数出，0~2 DATA:显示数据输入0~9999 9999 编写人：黄道斌编写日期： 2006/07/13 -------------------------------------*/-//led.v /*------------------------------------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : digital control options from the median, 0 ~ 2 DATA : data show that the importation of 0 ~ 9999 9999 prepared : Huang Daobin preparation date : 2006/07/13-------------------------------------*/
Platform: | Size: 1024 | Author: 黄道斌 | Hits:

[VHDL-FPGA-Verilog] verilogshejiMiLeJIEMAQI

Description: 用verilog设计密勒解码器一、题目：设计一个密勒解码器电路二、输入信号： 1． DIN：输入数据 2． CLK：频率为2MHz的方波，占空比为50％ 3． RESET：复位信号，低有效三、输入信号说明：输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成； A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。 B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保持“1”。 C：前5个时钟保持“0”，后面11个时钟保持“1”。改进密勒码编码规则如下：如果码元为逻辑“1”，用A信号表示。如果码元为逻辑“0”，用B信号表示，但以下两种特例除外：如果出现两个以上连“0”，则从第二个“0”起用C信号表示；如果在“通信起始位”之后第一位就是“0”，则用C信号表示，以下类推； “通信起始位”，用C信号表示； “通信结束位”，用“0”及紧随其后的B信号表示。 “无数据”，用连续的B信号表示。-err
Platform: | Size: 211968 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: VERILOG实现多时钟,可以应用于流水线.输入CLK,输出CLK1,CLK2,CLK3-Verilog realize multi-clock, can be applied to assembly line. Input CLK, the output CLK1, CLK2, CLK3
Platform: | Size: 1024 | Author: kaimen | Hits:

[SCM] elev

Description: Verilog 电梯控制器设计设计一个八层楼房自动电梯控制器，用八个 LED显示电梯行进过程，并有数码管显示电梯当前所在楼层位置，在每层电梯入口处设有请求按钮开关，请求按钮按下则相应楼层的LED 亮。用 CLK脉冲控制电梯运动，每来一个 CLK脉冲电梯升（降）一层。电梯到达有请求的楼层后，该层次的指示灯灭，电梯门打开（开门指示灯亮），开门 5 秒后，电梯门自动关闭，电梯继续运行。控制电路应能记忆所有楼层请求信号，并按如下运行规则依次相应：运行过程中先响应最早的请求，再响应后续的请求。如果无请求则停留当前层。如果有两个同时请求信号，则判断请求信号离当偍层的距离，距离近请求的先响应，再响应较远的请求。每个请求信号保留至执行后清除。 -err
Platform: | Size: 76800 | Author: Fly | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Platform: | Size: 129024 | Author: 623902748 | Hits:

[Software Engineering] median

Description: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Platform: | Size: 2048 | Author: 刘文英 | Hits:

[VHDL-FPGA-Verilog] clk_divider

Description: Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
Platform: | Size: 1024 | Author: h_j_tel | Hits:

[Other] clk_div

Description: 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
Platform: | Size: 199680 | Author: 颜爱良 | Hits:

[Other] verilog

Description: 设计可以对两个运动员赛跑计时的秒表:(1）只有时钟（clk）和一个按键（key），每按一次，key是持续一个时钟周期的高电平脉冲（2）秒表输出用0－59的整数表示（3）key：（A）按一下key，开始计数；（B）第一个运动员到终点时第二下key，记住时间，继续计数；（C）二个运动员到时按第三下key，停止计数；（D）然后按第四下key，秒表输出第一个运动员到终点的时间，即按第二下key时记住的计数值；（E）按第五下key，秒表清0。 -Design of the two athletes running time of the stopwatch: (1) Only the clock (clk) and a button (key), each time, key is continuing a clock cycle, high pulse (2) stopwatch output with 0-59 integer that (3) key: (A) Click the key, start counting (B) When the first player to finish under the second key, remember the time, continue to count (C) two players to press the third Under the key, stop counting (D) and then by the fourth under the key, stopwatch output of the first athletes to the end of the time, that is, the next key by the second count when remembered (E) by the fifth under the key, stopwatch clear 0.
Platform: | Size: 1024 | Author: gab | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1，无校验位；代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 通过 UART 读写 SDRAM verilog 源代码通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00：写数据 02：写个数 0011：写地址 1111 2222：写数据，是 16 bit，每写完一个数据，向串口发送 FF 回应；输出： FF FF 01 03 0044 01: 读sdram 03：读的个数 0044: 读的地址输出： xxxx xxxx xxxx sdram 在 0044 0045 0046 处的数据； sdram 使用的是 K4S161622D.pdf 系统时钟 25m，通过 PLL 得到 SDRAM clk 100m sdram controller clk 100m，前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
Platform: | Size: 14336 | Author: 周西东 | Hits:

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[VHDL-FPGA-Verilog] pcm

[VHDL-FPGA-Verilog] 8LEDverilog

[VHDL-FPGA-Verilog] verilogshejiMiLeJIEMAQI

[VHDL-FPGA-Verilog] clk_div

[SCM] elev

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] shifter

[Software Engineering] median

[VHDL-FPGA-Verilog] clk_divider

[Other] clk_div

[Other] verilog

[VHDL-FPGA-Verilog] sim_uart

[VHDL-FPGA-Verilog] sdram

[VHDL-FPGA-Verilog] clk

[VHDL-FPGA-Verilog] design-a-clk-system-by-verilogHDL

[VHDL-FPGA-Verilog] clk

[VHDL-FPGA-Verilog] CLK

[VHDL-FPGA-Verilog] clk

[OS program] clk-10divide

[VHDL-FPGA-Verilog] fnd-clk

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