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[Other resourcecic3s32

Description: 一个3阶的32位抽取的cic滤波器的verilog源代码
Platform: | Size: 1005 | Author: 岑楠 | Hits:

[Other resourcecic3s32

Description: 阶的32倍抽取cic滤波器verilog代码
Platform: | Size: 1000 | Author: zly | Hits:

[Communication-Mobilecic3s32

Description: 改进行级联CIC梳状滤波器,通带内平坦性好,带外抑制更好
Platform: | Size: 55643 | Author: 帅哥 | Hits:

[VHDL-FPGA-Verilogcic3s32

Description: 一个3阶的32位抽取的cic滤波器的verilog源代码-A 3-bands of the 32 samples CIC filter Verilog source code
Platform: | Size: 1024 | Author: 岑楠 | Hits:

[Other Embeded programcic3s32

Description: 阶的32倍抽取cic滤波器verilog代码-Order CIC filter 32 times the extraction Verilog code
Platform: | Size: 1024 | Author: zly | Hits:

[Communication-Mobilecic3s32

Description: 改进行级联CIC梳状滤波器,通带内平坦性好,带外抑制更好-To carry out cascade CIC comb filter, with passband flatness, and band rejection better
Platform: | Size: 55296 | Author: 帅哥 | Hits:

[Communication-Mobilecic3s32

Description: 本程序主要有三部分构成:首先是4个积分器部分,其次是抽取器部分实现32倍抽取,最后组成部分是4个梳状滤波器。该程序结构可节省4个32的延迟单元。-The program has three main parts: First, the integrator part 4, followed by the extraction device to achieve 32 times the extraction part, the final component of the four comb filter. The program structure can save 32 to delay unit 4.
Platform: | Size: 1024 | Author: 黄英 | Hits:

[VHDL-FPGA-Verilogcic3s32

Description: 3阶cic滤波器,16位输出,32倍降采样处理(The 3 order CIC filter, 16 bit output, 32 fold down sampling processing)
Platform: | Size: 1024 | Author: today_ztt | Hits:

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