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[Other] an391_performance_checksum

Description: checksum fpga verilog
Platform: | Size: 7642 | Author: fenghua | Hits:

[Other] an391_performance_checksum

Description: checksum fpga verilog
Platform: | Size: 7168 | Author: fenghua | Hits:

[VHDL-FPGA-Verilog] fast-crc.tar

Description: 一个verilog实现的crc校验，用于fpga实现，快速，准确有效-A Verilog realize the CRC checksum for the FPGA realization, rapid, accurate and effective
Platform: | Size: 1440768 | Author: 枫叶鹏 | Hits:

[VHDL-FPGA-Verilog] altera_avalon_checksum

Description: altera的avalon总线校验代码,是进行sopc开发的参考-altera the avalon bus check code, is to develop a reference SOPC
Platform: | Size: 12288 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] Serial_CRC

Description: CRC校验串行实现方法,verilog源码,利用反馈线性移位寄存器的方法,实现简单,适用于串行通信协议中的CRC校验.-CRC checksum method of serial realize, verilog source code, the use of linear feedback shift register method, the realization of simple serial communication protocol for the CRC checksum.
Platform: | Size: 1024 | Author: 徐亮 | Hits:

[Crack Hack] parallel_CRC

Description: CRC校验并行实现,Verilog源码.8位数据输入,实现速度快,适用与各种类型的器件.-Parallel Implementation of CRC checksum, Verilog source code .8-bit data input, to achieve fast, applicable with all types of devices.
Platform: | Size: 78848 | Author: 徐亮 | Hits:

[Windows Develop] crc_wizard_v1_1

Description: 用Verilog写的CRC校验程序 非常不错-Written using Verilog procedures are very good CRC Checksum
Platform: | Size: 486400 | Author: westspeed | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[Algorithm] verilog_multicrc

Description: 该文件为多种CRC校验的不同的verilog实现，开发平台为QUATUS2，可直接运行-The document for a variety of different CRC checksum Verilog realize, development platform for QUATUS2, can be directly run
Platform: | Size: 10240 | Author: 金智远 | Hits:

[assembly language] byte_crc

Description: 字节型CRC校验 采用verilog语言设计-Byte CRC checksum type design using Verilog language
Platform: | Size: 403456 | Author: 郭超勇 | Hits:

[Crack Hack] A-PAINLESS-GUIDE-TO-CRC-ERROR-DETECTION-ALGORITHMS

Description: A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC校验理论与实践的经典教程，Ross写的。-A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC checksum of the classic theory and practice tutorials, Ross wrote.
Platform: | Size: 184320 | Author: haoz | Hits:

[Communication] crc_check

Description: CRC校验，包括crc8_4、crc12_4、crc16_8、crc32_8-CRC checksum, including crc8_4, crc12_4, crc16_8, crc32_8
Platform: | Size: 4096 | Author: wl | Hits:

[Crack Hack] crc

Description: 这是CRC字符串校验的源码，可对字符串校验后输出校验码-This is the CRC checksum of the source string can be output after the string checksum validation code
Platform: | Size: 195584 | Author: ch | Hits:

[VHDL-FPGA-Verilog] eth_crc

Description: crc校验码Verilog 程序。此为4位并行crc——32校验。-crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
Platform: | Size: 2048 | Author: hepeng | Hits:

[VHDL-FPGA-Verilog] my

Description: 64位数据的CRC-32校验的，Verilog实现，算法并行优化-64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm
Platform: | Size: 133120 | Author: dowson | Hits:

[VHDL-FPGA-Verilog] crc_8

Description: 基于verilog的并行crc8的校验，已经仿真过，符合设计要求，可以拿去参考-Verilog a parallel crc8 checksum, already simulation, meet the design requirements, you can take reference
Platform: | Size: 1373184 | Author: 王诚 | Hits:

[VHDL-FPGA-Verilog] crc16-

Description: 本文档描述了一种CRC校验的方法，开发语言为verilog。程序自己写的，包括测试代码。欢迎参考-This document describes a CRC checksum method development language verilog. Write their own procedures, including test code. Welcome reference
Platform: | Size: 1024 | Author: 秦艳召 | Hits:

[VHDL-FPGA-Verilog] jiaoyan

Description: Verilog编写的crc16校验程序，为大家通信校验提供一种可靠的方法-Verilog prepared crc16 checksum procedure for everyone to provide a reliable communication method validation
Platform: | Size: 351232 | Author: 李子豪 | Hits:

[Other] CRC16_8

Description: 利用ISE软件采用Verilog HDL语言编写CRC码，每时钟处理8bit数据，在输入序列后最终加上16位校验码。-Using Verilog HDL language CRC code, 8bit data processing per clock, after the final of the input sequence plus 16 checksum.
Platform: | Size: 3329024 | Author: 刘璐 | Hits:

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