Description: Parallel Implementation of CRC checksum, Verilog source code .8-bit data input, to achieve fast, applicable with all types of devices.
- [VHDL_100Examples] - Beijing University Institute of ASIC des
- [sc] - Prepared using Verilog table tennis game
- [Serial_CRC] - CRC checksum method of serial realize, v
- [crc] - For 10M, 100M, 1000M Ethernet parallel C
- [crc16_ccitt] - crc_table.c is for reset seed (0000) crc
- [atm] - atm cell detection, CRC cyclical redunda
- [CRC] - Cyclic Redundancy Check realize Verilog
- [verilog_multicrc] - The document for a variety of different
- [CRC] - CRC code written in Verilog
- [RFC_1622_CRC16_m] - RFC1662 CRC-16 table generation and CRC
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