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[VHDL-FPGA-Verilog] IP_SPI

Description: spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers.
Platform: | Size: 344064 | Author: 李鸣 | Hits:

[VHDL-FPGA-Verilog] canbus_vhdl

Description: 使用方法： 1.拷贝到硬盘，用ISE打开工程文件即可。-Use : 1. Copy to the hard drive, use ISE project documents can be opened.
Platform: | Size: 862208 | Author: lious | Hits:

[Other] canvhdl

Description: can总线控制器的原代码，是用vhdl写的，我没有验证过，不保证正确性。可以作为参考。 -can Bus Controller's original code is written in vhdl, I have not tested, it does not guarantee accuracy. Can be used as reference.
Platform: | Size: 31744 | Author: 吴明诗 | Hits:

[VHDL-FPGA-Verilog] fpgalcddriver

Description: 基于FPGA液晶控制器设计与实现，采用VHDL硬件描述语言。-FPGA-based LCD controller design and implementation using VHDL hardware description language.
Platform: | Size: 92160 | Author: 张杰 | Hits:

[Parallel Port] Bidirectional-Bus

Description: 双向总线的VHDL源代码，已经通过编译，可以在此基础上改为单向总线。-Bi-directional bus VHDL source code, has passed the compiler can be changed on the basis of one-way bus.
Platform: | Size: 3072 | Author: 吴超 | Hits:

[VxWorks] 44b0basic

Description: 44b0/linux环境基本实验源码,包括helloworld,线程,串口,AD,DA,CAN总线,LED,电机,GPS,GPRS,键盘驱动等-Experimental 44b0/linux environmental source, including the helloworld, threading, serial, AD, DA, CAN bus, LED, motor, GPS, GPRS, keyboard-driven, etc.
Platform: | Size: 1690624 | Author: 打火石 | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 一个关于4CAN卡的硬件程序,用VHDL编写.就是4路CAN总线-4CAN card on the hardware procedures, prepared by VHDL. Is 4 CAN BUS
Platform: | Size: 624640 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] can_IPCORE

Description: CAN总线IPCORE，采用Verilog HDL语言实现。-CAN bus IPCORE, using Verilog HDL language.
Platform: | Size: 61440 | Author: feifei | Hits:

[VHDL-FPGA-Verilog] CAN_controller_ip

Description: 一个用硬件描述语言编写CAN总线控制器的IP，可以用在NIOS II上。-A hardware description language used CAN bus controller of the IP, can be used in the NIOS II.
Platform: | Size: 63488 | Author: 李建刚 | Hits:

[SCM] CAN_design

Description: 实现can总线的硬件布线图，在protel上直接打开即可，按此图的实物板已制出，可确保无误。-The realization of the hardware can bus wiring diagram, in Protel can directly open, this physical map has already been produced to ensure accuracy.
Platform: | Size: 100352 | Author: 高显忠 | Hits:

[SCM] source_code

Description: 一些源程序，主要包括CAN总线驱动、sdram VHDL实现、ucos2的移植、SDIO驱动、tcpip的实现、usb控制器代码、基于FPGA的雷达目标模拟器等-Some source code, including CAN bus driver, sdram VHDL implementation, ucos2 transplant, SDIO drivers, tcpip of implementation, usb controller code, based on the FPGA, such as radar target simulator
Platform: | Size: 6898688 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware description language code for the FPGA bus interface controller development
Platform: | Size: 862208 | Author: shigengxin | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[SCM] can

Description: can bus ctroller,the function of read and write-can bus contrller
Platform: | Size: 1024 | Author: qiufeng | Hits:

[VHDL-FPGA-Verilog] can_latest.tar

Description: VHDL/VERILOG FOR CAN BUS Core
Platform: | Size: 1176576 | Author: mss | Hits:

[VHDL-FPGA-Verilog] canbus

Description: CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
Platform: | Size: 863232 | Author: 张小琛 | Hits:

[VHDL-FPGA-Verilog] design-of-CAN-based-on-VHDL

Description: 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness
Platform: | Size: 2615296 | Author: chen xinwei | Hits:

[VHDL-FPGA-Verilog] can

Description: 一个典型的CAN总线的VHDL程序，非常有参考价值-A typical CAN bus VHDL program, a very valuable reference! !
Platform: | Size: 72704 | Author: 崔凯华 | Hits:
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