Description: 该压缩包中包括常见的超宽带通信的同步比特的搜索算法.-the compression package including common UWB bit synchronization algorithm for the search. Platform: |
Size: 1762 |
Author:zzq |
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Description: 该压缩包中包括常见的超宽带通信的同步比特的搜索算法.-the compression package including common UWB bit synchronization algorithm for the search. Platform: |
Size: 1024 |
Author:zzq |
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Description: 北邮通信仿真教程第10章的源程序，教程网上可以搜到，程序包括BPSK,QPSK的调制解调，载波同步，误比特率的计算等。-Beijing University of Posts and Telecommunications Communication Simulation Guide to Chapter 10 of the source, the Guide can be found online that included BPSK, QPSK modulation and demodulation, carrier synchronization, bit error rate calculation. Platform: |
Size: 12288 |
Author:到达 |
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Description: 基于VHDL语言的HDB3码编译码器的设计
HDB3 码的全称是三阶高密度双极性码，它是数字基带传输中的一种重要码型，具有频谱中无直流分量、能量集中、提取位同步信息方便等优点。HDB3 码是在AMI码(极性交替转换码)的基础上发展起来的，解决了AMI码在连0码过多时同步提取困难的问题-Based on the VHDL language code HDB3 codecs design HDB3 code name is the third-order high-density bipolar code, it is the digital base-band transmission an important pattern, with no DC component spectrum, energy concentration, extraction bit synchronization information, such as the advantages of convenience. HDB3 code is in the AMI code (alternating polarity conversion code) developed on the basis of resolving the AMI code 0 yards too much even when difficult issues simultaneously extract Platform: |
Size: 257024 |
Author:liangtao |
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Description: 本文是在FPGA下，实现的有关接收机位同步电路文章，介绍了实现的方法等。-This article is in the FPGA, the realization of the receiver bit synchronization circuit article introduces the realization of the methods. Platform: |
Size: 205824 |
Author:youyou |
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Description: 针对位同步问题，提出了一种基于基函数分解的开环位定时估计算法。该算法首先利用基函数分解的结果进行相关运算，将本地参考信号波形和接收信号波形的定时偏差缩小到T/4以内；再根据相关运算提供的角度信息进行精确的位同步估计。该算法不需要提取载波相位信息，复杂度较低。仿真结果表明该算法具有较好的估计精度-For bit synchronization, a basis function-based decomposition of the open-loop-bit timing estimation algorithm. The algorithm-based function decomposition of the first to use the results of operations related to the local reference signal received signal waveform and waveform timing deviation reduced to T/4 or less another operator in accordance with the relevant provision of accurate information-bit synchronous estimated. The algorithm does not require extraction of carrier phase information, low complexity. The simulation results show that the algorithm has better estimation accuracy Platform: |
Size: 429056 |
Author:luoluo |
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Description: 详细讲解了同步原理，包括载波同步、位同步、帧同步-Detailed account of the principle of synchronization, including the carrier synchronization, bit synchronization, frame synchronization Platform: |
Size: 307200 |
Author:wuqianye |
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Description: GMSK位同步的Gardner改进算法,是IEEE上很好的一篇文章-GMSK bit synchronization Gardner improved algorithm is very good IEEE on an article Platform: |
Size: 231424 |
Author:zhou minghui |
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Description: 很好的OFDM的基于MATLAB的仿真程序包，且包含了最终结果图.-montecarlo
type montecarlo in the command window and wait for a long time..
_simulation of the complete OFDM system.
_use of a very large file in order to get probabilities.
_loop over different value of the noise.
_compute the SNR for each value of the noise.
_provide the SNR/BER plot.
if you are in a rush : simulation_system !!
go into the right folder and type simulation_system in the command window.
_then type the value of the noise power (range = [-20,10])
_the function provides the channel estimation, the bit allocation,
and a plot illustrating the errors.
_this is a fast function (less pilot, no synchronization, small file). Platform: |
Size: 96256 |
Author:田静 |
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Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz Platform: |
Size: 2048 |
Author:张键 |
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Description: Matlab的OFDM在多径Rayleigh信道下的同步
1. 假设频率已同步，设计OFDM一种具体的采用循环前缀进行时间同步方法，用Simulink进行仿真，画出比特信噪比与捕获概率的关系曲线。
2. 设时间已同步，设计OFDM一种具体的采用循环前缀进行频率同步方法，用Simulink进行仿真，画出比特信噪比与频率同步误差的关系曲线.-Matlab-OFDM in multipath Rayleigh channel synchronization 1. Assume that the frequency has been synchronized, the design of a specific OFDM cyclic prefix for time synchronization method, using Simulink simulation to depict the bit signal to noise ratio and the capture probability curve. 2. Set up time is synchronized to design a specific OFDM cyclic prefix for frequency synchronization method, using Simulink simulation to depict the bit signal to noise ratio and frequency synchronization error of the curve. Platform: |
Size: 21504 |
Author:the13thstone |
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Description: 本人写的MSK解调位同步完整程序，基于QuartusII90环境，采用verilog语言编写，程序简练，可靠性高，而且暂用资源少，适合CPLD器件。文件包含仿真和说明，欢迎下载！-I write a complete program MSK demodulation bit synchronization, based on QuartusII90 environment, using verilog language, procedures, concise, high reliability, and the temporary use, fewer resources for CPLD devices. File contains the simulation and instructions, please download! Platform: |
Size: 320512 |
Author:Kerwin |
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Description: 各种同步实验及系统设计。包括：同步载波提取、帧同步信号提取实验、位同步信号提取实验以及衰落信道帧同步电路设计与实现和位同步的提取方法设计。-Various synchronization experiment and system design. Including: synchronous carrier extraction, frame synchronization signal extraction experiments, bit synchronization signal extraction experiment and fading channel frame synchronization circuit design and implementation and bit synchronization method of extracting the design. Platform: |
Size: 355328 |
Author:Kerwin |
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Description: dsss有关的位同步帧同步数字锁相法实现位同步-dsss the bit synchronization method to achieve frame synchronization bit synchronous digital lock Platform: |
Size: 1783808 |
Author:liufei |
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Description: qpsk完整解调，包括载波同步，位同步采用迟早门，载波同步采用判决反馈-qpsk complete demodulation, including the carrier synchronization, bit synchronization using the door sooner or later, the use of decision feedback carrier synchronization Platform: |
Size: 2048 |
Author:丁建 |
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Description: 在CAN总线中,位定时有一点小错误就会导致总线性能严重下降。虽然在许多情况下，位同步会修补由于位定时设置不当而产生的错误，但不能完全避免出错情况，并且在遇到两个或多个CAN节点同时发送的情况时，错误的采样点会使节点启动错误认可标志，使节点不能赢得总线上的任何活动。因此要分析、解决这样的错误就需要对CAN总线位定时中的位同步和CAN节点的工作过程有一个深入的了解。本文描述了CAN总线位同步的运行规则以及如何对位定时的参数进行设置。-In the CAN bus, there is a little bit timing errors will lead to a serious decline in bus performance. Although in many cases, bit synchronization bit timer settings will fix improper because of errors, but can not completely avoid error conditions, and in the event of two or more CAN nodes simultaneously send the case, the error of the sampling points will node startup error recognition signs, so that nodes can not win any activity on the bus. Therefore, to analyze and solve this error you need for the CAN bus bit timing and bit synchronization in CAN nodes have a working understanding of the process. This paper describes the operation of the CAN bus bit synchronization bit timing rules and how to set the parameters. Platform: |
Size: 28672 |
Author:陈晓楠 |
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Description: 全数字锁相环实现位同步，通过3个触发器实现码元的边沿提取。基带码采用M序列仿真。-DPLL to achieve bit synchronization, achieved through three trigger symbol of the edge extraction. Baseband codes using M-sequence simulation. Platform: |
Size: 569344 |
Author:林竹 |
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Search - bit synchronization