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[Other resource] vcpwmcpldcar

Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码
Platform: | Size: 959427 | Author: hxf | Hits:

[Other resource] keyboardScan

Description: PS2接口键盘扫描码截取电路，VHDL程序。该程序能够捕获PS2键盘按下的按键值，并将其扫描码转换成ASCII码。
Platform: | Size: 1386 | Author: 宁新 | Hits:

[VHDL-FPGA-Verilog] vcpwmcpldcar

Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码-vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code
Platform: | Size: 959488 | Author: hxf | Hits:

[VHDL-FPGA-Verilog] keyboardScan

Description: PS2接口键盘扫描码截取电路，VHDL程序。该程序能够捕获PS2键盘按下的按键值，并将其扫描码转换成ASCII码。-PS2 keyboard scan code interception interface circuit, VHDL procedures. The program can capture PS2 keyboard press the keys values and scan codes into ASCII code.
Platform: | Size: 1024 | Author: 宁新 | Hits:

[VHDL-FPGA-Verilog] ps2_keyboard

Description: ps2 keyboard verilog源代码,支持ascii码.扫描码输出,扩展键输出,按下及释放信息输出-ps2 keyboard verilog source code, to support the ascii code. scan code output, the expansion of key output, press and release the information output
Platform: | Size: 5120 | Author: 李志刚 | Hits:

[VHDL-FPGA-Verilog] PS2_LCD

Description: ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符
Platform: | Size: 344064 | Author: 张海风 | Hits:

[SCM] ps2_lcd

Description: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.
Platform: | Size: 9216 | Author: yuan | Hits:

[VHDL-FPGA-Verilog] vga_display

Description: VGA controller源码及显示汉字和ascii字符的c代码实例，已在DE2-70上实现-vga_controller source code and c code which can display chinese charactors and ASCII code on the VGA
Platform: | Size: 304128 | Author: | Hits:

[Embeded-SCM Develop] serial

Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 --划分为8个时隙以使通信同步. --程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome" --字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制 --数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at - PC machine on the installation of a serial debugging tools to verify the function of the procedure. - Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control - System, and 10 bit is a start bit, 8 data bits, 1 Ending - Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real - Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are - 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time - Is divided into eight time slots in order to enable synchronous communication. - Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome" - String (serial debug tools is set to accept by way of A
Platform: | Size: 65536 | Author: johnson | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ps2 vhdl 实现键盘输入 数码管显示ascii码-ps2 vhdl
Platform: | Size: 187392 | Author: 建宁 | Hits:

[Com Port] chuankoutongxin

Description: 串口通信的概念非常简单，串口按位（bit）发送和接收字节。尽管比按字节（byte）的并行通信慢，但是串口可以在使用一根线发送数据的同时用另一根线接收数据。它很简单并且能够实现远距离通信。比如IEEE488定义并行通行状态时，规定设备线总常不得超过20米，并且任意两个设备间的长度不得超过2米；而对于串口而言，长度可达1200米。典型地，串口用于ASCII码字符的传输。通信使用3根线完成：（1）地线，（2）发送，（3）接收。由于串口通信是异步的，端口能够在一根线上发送数据同时在另一根线上接收数据。其他线用于握手，但是不是必须的。串口通信最重要的参数是波特率、数据位、停止位和奇偶校验。-The concept of serial communication is very simple, serial by bit (bit) to send and receive bytes. Although more than by byte (byte) of parallel communication slow, but can use a serial line to send data at the same time another line to receive data. It is very simple and can achieve long-distance communications. For example, the definition of IEEE488 parallel access mode, the total line often provides equipment shall not be more than 20 meters, and between any two devices may not be more than two meters in length and in terms of the serial port, up to 1200 meters in length. Typically, serial code for the ASCII character transmission. 3 lines of communication to use to complete: (1) ground, (2) send, (3) to receive. Due to the asynchronous serial communication port to send data in a line at the same time another line to receive data. Other lines for the handshake, but not necessary. Serial communication the most important parameter is the baud rate, data bits, stop bits and parity.
Platform: | Size: 1024 | Author: zhendongzhao | Hits:

[Other] code

Description: This code for ASCII ALTERA
Platform: | Size: 4096 | Author: DI | Hits:

[VHDL-FPGA-Verilog] choosebcd

Description: 基于vhdl的BCD码转ASCII码的设计，已经经过调试，可直接使用-Vhdl code based on the BCD to ASCII code of the design, debugging has been directly used
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] ps2

Description: 采用sopc技术，nios2ide开发环境，实现nios对ps2键盘的控制，按键讲ascii码显示在led上-Using sopc technology, nios2ide development environment to achieve nios right ps2 keyboard control, key speakers led the ascii code is displayed in
Platform: | Size: 8153088 | Author: 蹇清平 | Hits:

[Driver Develop] keyboard_vhdl

Description: ps2 keyboard with encoding ascii code to 7-segments screeen. LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY klawa IS PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC SW : in std_logic_vector(4 downto 0) HEX1, HEX2, HEX0, HEX3, HEX4, HEX5, HEX6, HEX7 : out std_logic_vector(6 downto 0) ) end klawa architecture Behavioral of klawa is component keyboard PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) scan_ready : OUT STD_LOGIC ) END component -ps2 keyboard with encoding ascii code to 7-segments screeen. LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY klawa IS PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC SW : in std_logic_vector(4 downto 0) HEX1, HEX2, HEX0, HEX3, HEX4, HEX5, HEX6, HEX7 : out std_logic_vector(6 downto 0) ) end klawa architecture Behavioral of klawa is component keyboard PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) scan_ready : OUT STD_LOGIC ) END component
Platform: | Size: 637952 | Author: arekk | Hits:

[VHDL-FPGA-Verilog] rs232_20M_19200

Description: 这是 一个 串口 vhdl 程序 主要完成了他的收发ASCII文本的功能-this is a vhdl serial port program
Platform: | Size: 226304 | Author: qinjian | Hits:

[VHDL-FPGA-Verilog] lcdasegaled

Description: lcd显示 跑马灯显示 七段数码管计时 12232F是一种内置8192个16*16点汉字库和128个16*8点ASCII字符集图形点阵液晶显示器,它主要由行驱动器/ 列驱动器及128×32全点阵液晶显示器组成。可完成图形显示,也可以显示7.5×2个(16×16点阵)汉字.与外部CPU接口采用并行或串行方式控制。-lcd display Seven-Segment LED Display Marquee is a built-in timing 12232F 8192 16* 16 points and 128 Chinese character library 16* 8 ASCII character set dot matrix liquid crystal display, which is mainly from the line driver/line driver and 128 × 32 full dot matrix liquid crystal display components. Complete graphical display can also show 7.5 × 2 个 (16 × 16 dot) character. And the external CPU interface with parallel or serial control.
Platform: | Size: 1107968 | Author: wws | Hits:

[assembly language] UART_RS232(VHDL)

Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
Platform: | Size: 607232 | Author: 饕餮小宇 | Hits:

[VHDL-FPGA-Verilog] bin2ascii

Description: Bin to ascii converter, with leading zeros. Room for improvement, remove the leading zeros.
Platform: | Size: 9216 | Author: xenfranco | Hits:
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