Search - arbiter code

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[VHDL-FPGA-Verilog] arbiter

Description: VHDL源代码共享,资源多多共享,论坛上多多讨论!-VHDL source code sharing, sharing of resources a lot, a lot of discussion forums!
Platform: | Size: 1024 | Author: wangzhe | Hits:

[OpenGL program] pci_arbi_quicklogic

Description: PCI 仲裁代码/ PCI BUS ARBITER //WRITTEN BY MARIA GEORGE `include "c:\pasic\spde\data\macros.v" module Arbiter (REQ_, reset_, clk_in, frame_, irdy_, GNT_, adbus, cbe) parameter MASTERS = 6 //This code can handle a maximum of six masters.-pci_arb code / PCI BUS ARBITER //WRITTEN BY MARIA GEORGE `include "c:\pasic\spde\data\macros.v" module Arbiter (REQ_, reset_, clk_in, frame_, irdy_, GNT_, adbus, cbe) parameter MASTERS = 6 //This code can handle a maximum of six masters.
Platform: | Size: 3072 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter unit includes client and server units. Used for Arbitation of multipliers in Altera FPGA based project. The code supports several multipliers and several clients with different priorities.-Arbiter unit includes client and server units. Used for Arbitation of multipliers in Altera FPGA based project. The code supports several multipliers and several clients with different priorities.
Platform: | Size: 6144 | Author: d0238 | Hits:

[Other] PCI_BUS_ARBITER

Description: PCI仲裁器代码，用verilog硬件描述语言写的-PCI Arbiter code, written in verilog hardware description language
Platform: | Size: 2048 | Author: 小杨 | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[SCM] arbriter-full

Description: this code is arbiter verilog design code and with testcases.
Platform: | Size: 6144 | Author: Prasad | Hits:

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[Other] ahb_system_generator.tar

[VHDL-FPGA-Verilog] arbiter

[OpenGL program] pci_arbi_quicklogic

[VHDL-FPGA-Verilog] Arbiter

[Other] PCI_BUS_ARBITER

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

[SCM] arbriter-full

[Multi Monitor] Backoff-verilog

[e-language] arbiter

[VHDL-FPGA-Verilog] arbiter_ip

[Crack Hack] arbiter-code

[VHDL-FPGA-Verilog] arbitration

[VHDL-FPGA-Verilog] AHBArbiter

[VHDL-FPGA-Verilog] arb

[VHDL-FPGA-Verilog] ahb_system_generator_latest.tar

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