Search - alu verilog code

[Other resource] verilog实现ALU的源代码

Description: verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Platform: | Size: 1382 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog编写的alu模块-Verilog modules prepared by the ALU
Platform: | Size: 1024 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] verilog实现ALU的源代码

Description: verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Platform: | Size: 1024 | Author: 飞扬 | Hits:

[ARM-PowerPC-ColdFire-MIPS] signal_cpu_sort

Description: Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
Platform: | Size: 8192 | Author: 張大小 | Hits:

[ARM-PowerPC-ColdFire-MIPS] verilog

Description: 8bit alu use verilog hdl
Platform: | Size: 8192 | Author: 周微微 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4位ALU逻辑运算单元，可进行加法、减法、逻辑运算、移位等操作。-4 ALU logical operation unit, can be additive, subtraction, logic operations, shift and other operations.
Platform: | Size: 1024 | Author: 甲天下 | Hits:

[VHDL-FPGA-Verilog] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15360 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4bit ALU（运算逻辑单元）的设计给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码使用quartus编译 cpu中 alu的设计可作为课程设计的参考此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog code for alu in RISC processor
Platform: | Size: 1024 | Author: John jose | Hits:

[VHDL-FPGA-Verilog] alu

Description: 这是32位alu的代码，使用verilog写的，包含了简单的运算功能-This is a 32-bit alu code, use verilog to write, and includes a simple arithmetic functions
Platform: | Size: 1024 | Author: 杨恋 | Hits:

[Other] alu

Description: ALU modeling verilog codes and testbench
Platform: | Size: 545792 | Author: neorome | Hits:

[ELanguage] xilinx_primitives

Description: verilog code for alu
Platform: | Size: 47104 | Author: manish kumar | Hits:

[VHDL-FPGA-Verilog] alu_32_bit

Description: 一个Verilog语言写的３２位ＡＬＵ的源码。-A language written in Verilog source code for a 32-bit ALU.
Platform: | Size: 2048 | Author: sunny | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 算术逻辑部件的verilog代码，它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
Platform: | Size: 169984 | Author: 李鹏飞 | Hits:

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[Other resource] verilog实现ALU的源代码

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] verilog实现ALU的源代码

[ARM-PowerPC-ColdFire-MIPS] signal_cpu_sort

[ARM-PowerPC-ColdFire-MIPS] verilog

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] alu-div

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] alu

[Other] alu

[ELanguage] xilinx_primitives

[VHDL-FPGA-Verilog] alu_32_bit

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] pipelALU

[VHDL-FPGA-Verilog] ALU

[VHDL-FPGA-Verilog] [Source code] 32bit_ALU_code_verilog

[VHDL-FPGA-Verilog] ALU

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