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[VHDL-FPGA-Verilog] alu181

Description: alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Platform: | Size: 1024 | Author: 赵心 | Hits:

[VHDL-FPGA-Verilog] yetert

Description: This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
Platform: | Size: 458752 | Author: crion | Hits:

[VHDL-FPGA-Verilog] ALU_VHDL_code

Description: ALU逻辑运算单元计算器的VHDL源代码，已通过FGPA验证，绝对正确。-ALU ALU calculator VHDL source code has been verified by FGPA absolutely correct.
Platform: | Size: 5120 | Author: 周州 | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[VHDL-FPGA-Verilog] alu_32_bit

Description: 32位基本运算器的功能，加法，减法，或，异或，与等基本功能-32 basic calculator functions, addition, subtraction, or, XOR, and other basic functions
Platform: | Size: 2048 | Author: 张明亮 | Hits:

[Books] ALU

Description: verilog语言的运算器，包含基本的加减、移位、循环移位操作-verilog language calculator, including basic addition and subtraction, shift, rotate shift operation
Platform: | Size: 1024 | Author: Jerome | Hits:

[Other] alu

Description: 在可编程逻辑器件上实现一个运算器，可以进行3位二进制数（无符号数）的加减运算。-The realization of a calculator on a programmable logic device, can be three binary numbers (unsigned) addition and subtraction.
Platform: | Size: 35840 | Author: fan1p | Hits:

[Windows Develop] aa

Description: Verilog实现运算器ALU的编程，加减（16位）乘除（16*16，32/16）-Verilog to achieve calculator ALU programming, and (16) and (16*16, 32/16)
Platform: | Size: 13312 | Author: arvin | Hits:

[VHDL-FPGA-Verilog] 计算器

Description: 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)
Platform: | Size: 1024 | Author: 哈皮Q | Hits:

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