- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2017-12-22
- Downloads:
- 0 Times
- Uploaded by:
- 章浅
Description: Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 计算器.txt | 15903 | 2017-12-22 |
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