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[SourceCodealtera sdram controller

Description: altera sdram controller vhdl
Platform: | Size: 2365413 | Author: langzhongfeilang@126.com | Hits:

[Documentsaltera封装

Description: altera产品封装
Platform: | Size: 1810642 | Author: fengfengff | Hits:

[Documentsaltera的几种新型的FPGA的配置方法和使用心得.rar

Description: altera的几种新型的FPGA的配置方法和使用心得
Platform: | Size: 159242 | Author: changroc | Hits:

[Documents“Altera杯”第五届全国研究生电子设计竞赛样板

Description: “Altera杯”第五届全国研究生电子设计竞赛样板
Platform: | Size: 896669 | Author: wsshenjun | Hits:

[Documentsaltera signalTap逻辑分析仪

Description: Altera.FPGA入门及提高教程]SignalTap.II.逻辑分析
Platform: | Size: 42612594 | Author: wangzgah@126.com | Hits:

[SourceCodeAltera IP Core

Description: 15 Altera IP Core
Platform: | Size: 49033 | Author: mayli8 | Hits:

[Embeded-SCM DevelopAltera-NIOS32-V220

Description: 一个测试端口测试程序-A test port test procedures
Platform: | Size: 39936 | Author: 站长 | Hits:

[Embeded-SCM Developverilog实例 [43项]

Description: 嵌入式可编程器件CPLD的典型实例 压缩包,共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询,有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Platform: | Size: 181248 | Author: 吴旭辉 | Hits:

[Crack Hack硬件求解平方根

Description: 硬件求解平方根源代码加密 (硬件求解平方根的,将license添加到原有的MaxplusII或QuartusII的license中就可以直接使用,但源代码加密。altera提供 )-solving square root of the hardware encryption code (square root of the hardware solution will be added to the original license MaxplusII or Quartus II of the license which can be directly used, but the source code encryption. ALTERA provide)
Platform: | Size: 39936 | Author: | Hits:

[Linux-Unixisr_uart_example_code

Description: altera串口源代码程序-ALTERA source code procedures
Platform: | Size: 5120 | Author: 梁远 | Hits:

[Embeded-SCM Developaltera

Description: FPGA研讨会的一些问题集!-some of the problems set!
Platform: | Size: 398336 | Author: 林建加 | Hits:

[DocumentsALTERA FPGA特殊管脚说明

Description: FPGA特殊管脚说明-special note
Platform: | Size: 12288 | Author: 王进 | Hits:

[VHDL-FPGA-Verilogmc8051_cyclone_nios

Description: 增强型8051的VHDL源代码,两个周期执行一条指令,仿真工具为Modelsim,开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
Platform: | Size: 2000896 | Author: 柳如飞 | Hits:

[VHDL-FPGA-Verilogtiny16cpu_maxII

Description: 这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核,文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
Platform: | Size: 240640 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilogtwo_d_dct_serial

Description: altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码,语言是:verilog 性能不错,不过资源消耗有点大,可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be used to transform learning polynomial algorithm DCT
Platform: | Size: 24576 | Author: 猪猪 | Hits:

[Embeded-SCM Developperl561src

Description: Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB开发--Altera recommends the following system configuration:* Pentium II 400 with 512-MB system memory (faster systems give better software performance)* SVGA monitor* CD-ROM drive* One or more of the following I/O ports:- USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit- Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables- Serial port for MasterBlaster communications cable* TCP/IP networking protocol installed* Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP* Internet Explorer 5.0 or later Memory & Disk Space Requirements USB development
Platform: | Size: 7300096 | Author: 周元平 | Hits:

[VHDL-FPGA-Verilogsopc

Description: altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
Platform: | Size: 8863744 | Author: 刘吉 | Hits:

[ARM-PowerPC-ColdFire-MIPSnios_tutorial

Description: altera nois cpu.Very good.
Platform: | Size: 445440 | Author: 张卫 | Hits:

[VHDL-FPGA-Verilogcolor_bar

Description: 使用vhdl语言在altera公司的up3板上产生vga信号,里面有详细的解析和说明,是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[VHDL-FPGA-Verilogaltera的IP源码

Description: Altera的IP源码8259,只需打开就能实现-Altera IP source 8259, will be realized only open
Platform: | Size: 149504 | Author: 王天权 | Hits:
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