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[Otherahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[VHDL-FPGA-Verilogahb_master1

Description: this is a code of AMBA AHB master protocol in verilog
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilogtb_ahb_master

Description: this is a AMBA AHB code for master.
Platform: | Size: 1024 | Author: bhaskar | Hits:

[VHDL-FPGA-Verilogmasterdecoder

Description: AHB总线协议 Master实现代码,对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[VHDL-FPGA-Verilogahblitemaster

Description: ahb master for single state representation code
Platform: | Size: 1024 | Author: Leela | Hits:

[VHDL-FPGA-VerilogAMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-VerilogAHB

Description: AMBA - AHB MASTER VERILOG CODE (UNCHECKED)
Platform: | Size: 15360 | Author: ilakiyareddy | Hits:

[ELanguage1

Description: AHB MASTER vhdl code and rtl schematic. dhasu code he bidu check kl lo bhle hi
Platform: | Size: 5120 | Author: ashu | Hits:

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