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Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must
be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
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Size: 269312 |
Author: 木石 |
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Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
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Size: 540672 |
Author: Bill Guan |
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Description: this is a code of AMBA AHB master protocol in verilog
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Size: 1024 |
Author: bhaskar |
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Description: this is a AMBA AHB code for master.
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Size: 1024 |
Author: bhaskar |
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Description: amba ahb master decoder
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Size: 1024 |
Author: bhaskar |
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Description: AHB总线协议 Master实现代码,对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
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Size: 1024 |
Author: 龙的传人 |
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Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
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Size: 17408 |
Author: jinjin |
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Description: AHB master 关于ahb总线协议中的master的encode -AHB master
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Size: 1024 |
Author: ray |
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Description: Generic AHB Master to all AHB transations
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Size: 2048 |
Author: Vbhat |
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Description: its shows the ip of amba ahb master in vhdl
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Size: 23552 |
Author: sachin |
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Description: 比较好的Verilog实现的AHB master。-Better AHB Verilog realization of the master.
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Size: 1024 |
Author: 冯磊 |
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Description: AMBA - AHB MASTER VERILOG CODE (UNCHECKED)
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Size: 15360 |
Author: ilakiyareddy |
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Description: ahb system generator
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Size: 268288 |
Author: Charlie Wang
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Description: AHB总线接口描述,MASTER的接口描述,AMB总线协议(AHB bus interface description, MASTER interface description, AMB bus protocol)
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Size: 4096 |
Author: 小萌子
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Description: verilog实现AHB总线上的主从控制,在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
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Size: 36864 |
Author: 落叶无情1992
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Description: amba ahb master generator by using verilog
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Size: 268288 |
Author: GADDAM
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Description: ahb to apb master and slave
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Size: 3072 |
Author: Sheth |
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Description: ahb to apb master verification
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Size: 2403328 |
Author: Sheth |
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Description: verilog ahb master and slave
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Size: 31744 |
Author: chandu1212 |
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Description: ahb master行为级模型,ahb slave模型(AHB master behavior level model, AHB slave model)
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Size: 2048 |
Author: 鱼在在藻 |
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