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[Other] EMCRYPTCHIPFORFPGA

Description: 基于FPGA加密芯片设计论文（AES和DES算法）-FPGA-based encryption chip design thesis (AES and DES algorithm)
Platform: | Size: 1068032 | Author: David | Hits:

[Crack Hack] aes_encryption

Description: aes加密算法的VHDL代码实现，在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Platform: | Size: 6144 | Author: stym_001 | Hits:

[Crack Hack] RIJNDAEL_DE_TOP

Description: AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
Platform: | Size: 19456 | Author: 刘文庆 | Hits:

[Crack Hack] aes

Description: aes加密算法实现，经过FPGA验证的！-aes encryption algorithm, after FPGA validation!
Platform: | Size: 6144 | Author: guochao | Hits:

[Crack Hack] khalil2006_true_random_number_generator

Description: a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are required to generate public/private key pairs for asymmetric algorithm such as RSA and symmetric algorithm such as AES.
Platform: | Size: 418816 | Author: Hassan Abdelaziz | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[Software Engineering] platforms

Description: A Pipelined Implementation of AES for Altera FPGA platforms.doc
Platform: | Size: 86016 | Author: Mohammad | Hits:

[VHDL-FPGA-Verilog] aesencryption

Description: Aes encryption on Fpga
Platform: | Size: 4096 | Author: Ibrahim | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[VHDL-FPGA-Verilog] aes

Description: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Platform: | Size: 87040 | Author: dinxj | Hits:

[VHDL-FPGA-Verilog] aescore

Description: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Platform: | Size: 195584 | Author: 李华 | Hits:

[Embeded-SCM Develop] FPGA

Description: 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code description of the design process, operation circuit modeling, algorithm programming
Platform: | Size: 3852288 | Author: betty | Hits:

[VHDL-FPGA-Verilog] FPGA_128_AES_decryption

Description: 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
Platform: | Size: 17012736 | Author: Vlog | Hits:

[VHDL-FPGA-Verilog] AES_test

Description: verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
Platform: | Size: 112640 | Author: zhongpeng | Hits:

[VHDL-FPGA-Verilog] xapp514_aes3-audio

Description: DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
Platform: | Size: 4483072 | Author: dcshl | Hits:

[VHDL-FPGA-Verilog] 09912007AEScoremodules

Description: aes description architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
Platform: | Size: 6144 | Author: tarang | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
Platform: | Size: 133120 | Author: weipingzhang | Hits:

[VHDL-FPGA-Verilog] aes

Description: verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
Platform: | Size: 7168 | Author: xie | Hits:

[File Format] AES-FPGA

Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
Platform: | Size: 191488 | Author: Eric | Hits:

[VHDL-FPGA-Verilog] aes-project-master

Description: aes project vhdl FPGA
Platform: | Size: 1096704 | Author: Nguyen Nam | Hits:
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