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Title: aescore Download
 Description: FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
 Downloaders recently: [More information of uploader watermanhua]
 To Search: VHDL code of AES aes verilog code Verilog AES
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  • [LIP1611CORE_AES128_SEC_UWB] - AES 128 Synthesisable RTL code
  • [aes] - The program is written using xilinx envi
  • [USB2.0examples] - usb 2.0 example on xilinx board... it us
File list (Check if you may need any files): 
aes core\aes.pdf
........\..._core\bench\verilog\test_bench_top.v
........\........\doc\aes.pdf
........\........\rtl\verilog\aes_cipher_top.v
........\........\...\.......\aes_inv_cipher_top.v
........\........\...\.......\aes_inv_sbox.v
........\........\...\.......\aes_key_expand_128.v
........\........\...\.......\aes_rcon.v
........\........\...\.......\aes_sbox.v
........\........\...\.......\timescale.v
........\........\...\.......\transcript
........\........\sim\rtl_sim\bin\Makefile
........\........\...\.......\run\waves\waves.do
........\........\.yn\bin\comp.dc
........\........\...\...\design_spec.dc
........\........\...\...\lib_spec.dc
........\........\...\...\read.dc
........\........\vim_session.vim
........\aes_core.tar.gz
........\OPENCORES.files\dotty.gif
........\...............\title_logo.gif
........\OPENCORES.htm
........\aes_core\sim\rtl_sim\run\waves
........\........\...\.......\bin
........\........\...\.......\run
........\........\bench\verilog
........\........\rtl\verilog
........\........\sim\rtl_sim
........\........\.yn\bin
........\........\bench
........\........\doc
........\........\rtl
........\........\sim
........\........\syn
........\aes_core
........\OPENCORES.files
aes core

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