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[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[VHDL-FPGA-Verilog] ADDER

Description: 经过精心设计的加法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed adder code, and FPGA hardware platform and tested
Platform: | Size: 1024 | Author: hewg | Hits:

[VHDL-FPGA-Verilog] VHDL-ADDER

Description: VHDL的N位加法器，非常的好用，经过仿真验证的！-VHDL N-bit adder, very easy to use, after the simulation!
Platform: | Size: 1024 | Author: 郭荣天 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 高达16位加法器的实现，工作环境在ISE，modesim，该例程较为详细！-Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!
Platform: | Size: 51200 | Author: 马高望 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 加法器可做4BIT的運算用直接語言撰寫-Adder computing can 4BIT
Platform: | Size: 313344 | Author: 劉家亦 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 采用加法树流水线乘法构造八位乘法器，并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
Platform: | Size: 1236992 | Author: 张炳良 | Hits:

[VHDL-FPGA-Verilog] adder

Description: verilog 加法器设计在modelsim下方针-verilog adder
Platform: | Size: 1039360 | Author: 兰书明 | Hits:

[MiddleWare] ADDER

Description: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
Platform: | Size: 278528 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] ADDER

Description: simple 16-bit CSA Adder
Platform: | Size: 65536 | Author: calvin | Hits:

[VHDL-FPGA-Verilog] adder

Description: 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路-A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules
Platform: | Size: 157696 | Author: 哈哈 | Hits:

[MPI] Parallel-adder

Description: 并行加法器是一种数位电路，其可进行数字的加法计算。在现代的电脑中，加法器存在于算术逻辑单元（ALU）之中。加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。-Parallel adder is a digital circuit, which can be calculated the number of addition. In the modern computer, adder exists in the arithmetic logic unit (ALU) into. Adder can be used to express a variety of values, such as: BCD, plus three yards, the major is based on a binary adder for computing.
Platform: | Size: 3072 | Author: jlz | Hits:

[Other] adder

Description: 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
Platform: | Size: 38912 | Author: zhaozimou | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

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[Documents] ripple-lookahead-carryselect-adder

[VHDL-FPGA-Verilog] ADDER

[VHDL-FPGA-Verilog] VHDL-ADDER

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] adder

[MiddleWare] ADDER

[VHDL-FPGA-Verilog] ADDER

[VHDL-FPGA-Verilog] adder

[MPI] Parallel-adder

[Other] adder

[VHDL-FPGA-Verilog] Floating-Point-Adder

[VHDL-FPGA-Verilog] floating-point-adder

[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder

[VHDL-FPGA-Verilog] 32-rip-adder

[Embeded-SCM Develop] 16-bit-adder

[Software Engineering] A-New-Reversible-Design-of-BCD-Adder

[VHDL-FPGA-Verilog] Optimized-design-of-BCD-adder-and-Carry

[VHDL-FPGA-Verilog] Adder and Counter VHDL

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